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ADAU1373BCBZ-R7 数据表(PDF) 54 Page - Analog Devices |
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ADAU1373BCBZ-R7 数据表(HTML) 54 Page - Analog Devices |
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54 / 296 page  ADAU1373 Rev. 0 | Page 54 of 296 SERIAL DATA INPUT/OUTPUT FORMATS The flexible serial data input and output ports of the ADAU1373 can be set to accept or transmit data in 2-channel format. Data is processed in twos complement, MSB first format. The left channel data field always precedes the right channel data field in 2-channel streams. The digital audio input can support the following audio formats: • I2S mode • Left justified • Right justified • Digital signal processor (DSP) mode The mode selection is performed by writing to the FORMATx bits (Bits[1:0]) of the digital audio interface settings registers (Register 0x44, Register 0x45, and Register 0x46). All modes are MSB first and operate with data of 16 bits to 32 bits. The serial data clocks must be synchronous with the ADAU1373 master clock input. The LRCLKx (Ball D3, Ball E2, and Ball F1) and BCLKx (Ball D2, Ball E4, and Ball F2) pins are used to clock both the serial input and output ports. The ADAU1373 can be set as the master or the slave in a system. See Figure 98 to Figure 102 for the proper configurations for standard audio data formats. MSB LEFT CHANNEL LSB MSB RIGHT CHANNEL LSB 1/ fS LRCLKx BCLKx SDATAINx, SDATAOUTx Figure 98. I2S Mode—16 Bits to 24 Bits per Channel LEFT CHANNEL MSB LSB MSB RIGHT CHANNEL LSB 1/ fS LRCLKx BCLKx SDATAINx, SDATAOUTx Figure 99. Left-Justified Mode—16 Bits to 24 Bits per Channel LRCLKx BCLKx SDATAINx, SDATAOUTx LEFT CHANNEL MSB LSB MSB RIGHT CHANNEL LSB 1/ fS Figure 100. Right-Justified Mode—16 Bits to 24 Bits per Channel 1/ fS LEFT CHANNEL RIGHT CHANNEL SDATAINx/ SDATAOUTx BCLKx LRCLKx 12 3 N N 1 2 3 Figure 101. DSP/Pulse Code Modulation (PCM) Mode Audio Interface Submode 1 (SM1), Register 0x44 to Register 0x46, Bit LRPx = 0 1/ fS LEFT CHANNEL RIGHT CHANNEL SDATAINx/ SDATOUTx BCLKx LRCLKx 123 N 1 2 N 3 FALLING EDGE CAN OCCUR ANYWHERE IN THIS AREA Figure 102. DSP/PCM Mode Audio Interface Submode 2 (SM2), Register 0x44 to Register 0x46, Bit LRPx = 1 |
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