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ADAU1373BCBZ-R7 数据表(PDF) 18 Page - Analog Devices

部件名 ADAU1373BCBZ-R7
功能描述  Low Power Codec with Speaker and Headphone Amplifier
PDF  296 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1373BCBZ-R7 数据表(HTML) 18 Page - Analog Devices

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ADAU1373
Rev. 0 | Page 18 of 296
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDDx = 1.8 V ± 10%.
Table 6.
Limit
Parameter
tMIN
tMAX
Unit
Description
MASTER CLOCK
Duty Cycle
45
55
%
SERIAL PORT
tBIL
5
ns
BCLKx pulse width low
tBIH
5
ns
BCLKx pulse width high
tLIS
5
ns
LRCLKx setup; time to BCLK rising
tLIH
5
ns
LRCLKx hold; time from BCLK rising
tSIS
5
ns
DAC_SDATA setup; time to BCLK rising
tSIH
5
ns
DAC_SDATA hold; time from BCLK rising
tSODM
50
ns
ADC_SDATA delay; time from BCLK falling in master mode
I2C PORT
fSCL
400
kHz
SCL frequency
tSCLH
0.6
μs
SCL high
tSCLL
1.3
μs
SCL low
tSCS
0.6
μs
Setup time; relevant for repeated start condition
tSCH
0.6
μs
Hold time; after this period of time, the first clock is generated
tDS
100
ns
Data setup time
tDH
5
ns
Data hold time
tSCR
300
ns
SCL rise time
tSCF
300
ns
SCL fall time
tSDR
300
ns
SDA rise time
tSDF
300
ns
SDA fall time
tBFT
0.6
μs
Bus-free time; time between stop and start
DIGITAL MICROPHONE
RL = 1 MΩ, CL = 14 pF
tDCF
10
ns
Digital microphone clock fall time
tDCR
10
ns
Digital microphone clock rise time
tDDV
22
30
ns
Digital microphone delay time for valid data
tDDH
0
12
ns
Digital microphone delay time for data, three-stated



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