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ADAU1373BCBZ-R7 数据表(PDF) 129 Page - Analog Devices |
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ADAU1373BCBZ-R7 数据表(HTML) 129 Page - Analog Devices |
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129 / 296 page  ADAU1373 Rev. 0 | Page 129 of 296 PWDN_CTRL1 REGISTER Address: 0x25, Reset: 0x00, Name: PWDN_CTRL1 Power-Down Block Control 1 Table 71. Bit Descriptions for PWDN_CTRL1 Bits Bit Name Settings Description Reset Access 7 LADCPDB Right Channel ADC Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 6 RADCPDB Left Channel ADC Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 5 MICB2PDB Microphone Bias 2 Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 4 MICB1PDB Microphone Bias 1 Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 3 AIN4PDB Analog Input 4 Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 2 AIN3PDB Analog Input 3 Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 1 AIN2PDB Analog Input 2 Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 0 AIN1PDB Analog Input 1 Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up |
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