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ADAU1373BCBZ-R7 数据表(PDF) 139 Page - Analog Devices |
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ADAU1373BCBZ-R7 数据表(HTML) 139 Page - Analog Devices |
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139 / 296 page  ADAU1373 Rev. 0 | Page 139 of 296 PLLB_CTRL1 REGISTER Address: 0x30, Reset: 0x00, Name: PLLB_CTRL1 PLLB Fractional Mode Denominator M High Byte Table 82. Bit Descriptions for PLLB_CTRL1 Bits Bit Name Settings Description Reset Access [7:0] PLLB_M_HI Denominator of the Fractional PLLB MSB. PLLB Fractional Mode Denominator M upper byte. 0x00 RW PLLB CTRL2 REGISTER Address: 0x31, Reset: 0x00, Name: PLLB_CTRL2 PLLB Fractional Mode Denominator M Lower Byte Table 83. Bit Descriptions for PLLB_CTRL2 Bits Bit Name Settings Description Reset Access [7:0] PLLB_M_LO Denominator of the Fractional PLLB LSB. PLLB Fractional Mode Denominator M lower byte. 0x00 RW PLLB_CTRL3 REGISTER Address: 0x32, Reset: 0x00, Name: PLLB_CTRL3 PLLB Fractional Mode N Table 84. Bit Descriptions for PLLB_CTRL3 Bits Bit Name Settings Description Reset Access [7:0] PLLB_N_HI Numerator of the fractional PLLB. PLLB Fractional Mode Numerator N upper byte. 0x00 RW |
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