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ADAU1373BCBZ-R7 数据表(PDF) 202 Page - Analog Devices |
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ADAU1373BCBZ-R7 数据表(HTML) 202 Page - Analog Devices |
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202 / 296 page ![]() ADAU1373 Rev. 0 | Page 202 of 296 DRC1_CTRL12 REGISTER Address: 0x8B, Reset: 0x7A, Name: DRC1_CTRL12 DRC1 Noise Gate Hold Time and Normal Operation Hold Time Setting Table 162. Bit Descriptions for DRC1_CTRL12 Bits Bit Name Settings Description Reset Access [7:4] DRCHTNOR DRC1 Hold Time for Normal Operation. 0x7 RW 0000 0 ms 0001 0.67 ms 0010 1.34 ms 0011 2.68 ms 0100 5.36 ms 0101 10.72 ms 0110 21.44 ms 0111 42.88 ms (default) 1000 85.76 ms 1001 171.52 ms 1010 341.33 ms 1011 686 ms 1100 1.37 sec 1101 Reserved 1110 Reserved 1111 Reserved [3:0] DRCHTNG DRC1 Hold Time for Noise Gating. 0xA RW 0000 0 ms 0001 0.67 ms 0010 1.34 ms 0011 2.68 ms 0100 5.36 ms 0101 10.72 ms |
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