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ADAU1373BCBZ-R7 数据表(PDF) 213 Page - Analog Devices |
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ADAU1373BCBZ-R7 数据表(HTML) 213 Page - Analog Devices |
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213 / 296 page ![]() ADAU1373 Rev. 0 | Page 213 of 296 DRC2_CTRL10 REGISTER Address: 0x99, Reset: 0xC0, Name: DRC2_CTRL10 DRC2 Threshold Point Y4 on Y-Axis (Output Level) Table 176. Bit Descriptions for DRC2_CTRL10 Bits Bit Name Settings Description Reset Access [7:0] DRCTHY4 DRC2 Y-Axis Threshold 4. 0xC0 RW 00000000 0 dB 00000001 −0.5 dB 00000010 −1 dB xxxxxxxx 0.5 dB step size 11000000 −96 dB (default) DRC2_CTRL11 REGISTER Address: 0x9A, Reset: 0x88, Name: DRC2_CTRL11 DRC2 Gain Smoothing Attack and Decay Time Setting |
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