AD9577BCPZ-R7 datasheet(29/44 Pages) AD

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Data Sheet

AD9577

Rev. 0 | Page 29 of 44

FUNCTIONAL DESCRIPTION

On the AD9577, parameters can be programmed over an I2C

bus to provide custom output frequencies, output formats, and

feature selections. However, this programming must be repeated

after every power cycle of the part.

The AD9577 contains two PLLs, PLL1 and PLL2, used for

independent clock frequency generation, as shown in Figure 32.

A shared crystal oscillator and reference clock input cell drive

both PLLs. The reference clock of the PLLs can be selected as

either the crystal oscillator output or the reference input clock.

A reference divider precedes each PLL. When the crystal oscillator

input is selected, these dividers must be set to divide by 1. When

the reference input is selected, these dividers can be set to

divide by 1 or divide by 2, provided that the resulting input

frequency to the PLLs is within the permitted 19.44 MHz to

27 MHz range. Both reference dividers are set to divide by the

same value. Each PLL drives two output channels, producing

four output ports in total for the IC. Each output channel

consists of a VCO divider block, followed by an output divider

block. The output divider blocks each drive with an output

buffer port. Each output buffer port can be configured as a

differential LVDS output, a differential LVPECL output, or two

LVCMOS outputs. Additionally, a CMOS-buffered version

reference clock frequency is available.

The upper PLL in Figure 32, PLL1, is an integer-N PLL. By

setting the feedback divider value (Na), the VCO output

frequency can tuned over the 2.15 GHz to 2.55 GHz range to

integer multiples of the PFD input frequency. By setting each of

the VCO divider (V0 and V1) and output divider (D0 and D1)

values, the VCO frequency can be divided down to the required

output frequency, independently, for each of the output ports,

OUT0 and OUT1. The loop filter required for this PLL is

integrated on chip.

The lower PLL in Figure 32, PLL2, is a fractional-N PLL. This

PLL can optionally operate as an integer-N PLL for optimum

jitter performance. By setting the feedback divider value (Nb)

and the Σ-Δ modulator fractional (FRAC) and modulus (MOD)

values, the VCO output frequency can tune over the 2.15 GHz

to 2.55 GHz range. The VCO frequency is a fractional multiple

of the PFD input frequency. In this way, the VCO frequency can

tune to obtain frequencies that are not constrained to integer

multiples of the PFD frequency. By setting each of the VCO divider

(V2 and V3) and output divider (D2 and D3) values, the VCO

frequency can be divided down to the required output frequency,

independently, for each of the output ports, OUT2 and OUT3.

The loop filters required for this PLL are integrated on chip.

The PLL2 can operate to modulate the output frequency between its

nominal value and a value that is up to −0.5% lower. This provides

spread spectrum modulation up to −0.5% downspread. Spread

spectrum frequency modulation can reduce the peak power output

of the clock source and any circuitry that it drives and lead to

reduced EMI emissions. In the AD9577, the frequency modulation

profile is triangular. The modulation frequency and modulation

range parameters are all programmable.

Both PLLs can be programmed to generate a second independent

frequency map under the control of the MARGIN pin. This

feature can be used to test the frequency robustness of a system.

REFERENCE INPUT AND REFERENCE DIVIDERS

The reference input section is shown in Figure 34. When the

REFSEL pin is pulled high, the crystal oscillator circuit is enabled.

The crystal oscillator circuit needs an external crystal cut to

resonate in fundamental mode in the 19.44 MHz to 27 MHz

range, with 25 MHz being used in most networking applications.

The total load capacitance presented to the crystal should add

up to 14 pF. In the example shown in Figure 34, parasitic trace

capacitance of 1.5 pF and an AD9577 input pin capacitance of

1.5 pF are assumed, with the series combination of the two

22 pF capacitances providing an additional 11 pF. When the

REFSEL pin is pulled low, the crystal oscillator powers down,

and the REFCLK pin must provide a good quality reference clock

instead. Either a dc-coupled LVCMOS level signal or an ac-coupled

square wave can drive this single-ended input, provided that an

external potential divider is used to bias the input at VS/2.

The output of the crystal oscillator and reference input circuitry

is routed to a reference divider circuit to further divide down

the reference input frequency to the PLLs by 1 or 2. When the

crystal oscillator circuit is used, the dividers must be set to

divide by 1. The input frequency to the PLLs must be in the

19.44 MHz to 27 MHz range. The divide ratio is set to 1 by

programming the value of R, Register G0[1], to 0. The divide

ratio is set to 2 by programming the value of R to 1.

XTAL

OSC

DIVIDE

1 OR 2

TO PLLs

REFCLK

REFSEL

22pF

Figure 34. Reference Input Section and Reference Dividers

Table 17. REFSEL (Pin 9) Definition

REFSEL

Reference Source

REFCLK input

Crystal oscillator

Table 18. Reference Divider Setting

R, Register G0[1]

Reference Divide Ratio

Divide by 1

Divide by 2

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