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AD9577BCPZ-R7 数据表(PDF) 8 Page - Analog Devices

部件名 AD9577BCPZ-R7
功能描述  Clock Generator with Dual PLLs
PDF  44 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9577BCPZ-R7 数据表(HTML) 8 Page - Analog Devices

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AD9577
Data Sheet
Rev. 0 | Page 8 of 44
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments1
Phase Noise (156.25 MHz CMOS Output)
Nb = 100, Vx = 4, Dx = 4, fPFD = 25 MHz
@ 1 kHz
−113
dBc/Hz
@ 10 kHz
−119
dBc/Hz
@ 100 kHz
−123
dBc/Hz
@ 1 MHz
−145
dBc/Hz
@ 10 MHz
−154
dBc/Hz
@ 30 MHz
−155
dBc/Hz
Phase Noise (155.52 MHz LVPECL Output)
Nb = 112, Vx = 2, Dx = 7, fPFD = 19.44 MHz
@ 1 kHz
−112
dBc/Hz
@ 10 kHz
−118
dBc/Hz
@ 100 kHz
−126
dBc/Hz
@ 1 MHz
−147
dBc/Hz
@ 10 MHz
−155
dBc/Hz
@ 30 MHz
−156
dBc/Hz
Phase Noise (622.08 MHz LVPECL Output)
Nb = 128, Vx = 2, Dx = 2, fPFD = 19.44 MHz
@ 1 kHz
−100
dBc/Hz
@ 10 kHz
−106
dBc/Hz
@ 100 kHz
−112
dBc/Hz
@ 1 MHz
−134
dBc/Hz
@ 10 MHz
−149
dBc/Hz
@ 30 MHz
−150
dBc/Hz
Phase Noise (155.52 MHz LVDS Output)
Nb = 112, Vx = 2, Dx = 7, fPFD = 19.44 MHz
@ 1 kHz
−113
dBc/Hz
@ 10 kHz
−118
dBc/Hz
@ 100 kHz
−126
dBc/Hz
@ 1 MHz
−145
dBc/Hz
@ 10 MHz
−154
dBc/Hz
@ 30 MHz
−155
dBc/Hz
Phase Noise (622.08 MHz LVDS Output)
Nb = 128, Vx = 2, Dx = 2, fPFD = 19.44 MHz
@ 1 kHz
−101
dBc/Hz
@ 10 kHz
−106
dBc/Hz
@ 100 kHz
−112
dBc/Hz
@ 1 MHz
−133
dBc/Hz
@ 10 MHz
−148
dBc/Hz
@ 30 MHz
−150
dBc/Hz
Phase Noise (155.52 MHz CMOS Output)
Nb = 112, Vx = 2, Dx = 7, fPFD = 19.44 MHz
@ 1 kHz
−113
dBc/Hz
@ 10 kHz
−118
dBc/Hz
@ 100 kHz
−126
dBc/Hz
@ 1 MHz
−146
dBc/Hz
@ 10 MHz
−155
dBc/Hz
@ 30 MHz
−155
dBc/Hz
1 x indicates either 2 or 3 for any given test condition.



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