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AD9577BCPZ-R7 数据表(PDF) 27 Page - Analog Devices

部件名 AD9577BCPZ-R7
功能描述  Clock Generator with Dual PLLs
PDF  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9577BCPZ-R7 数据表(HTML) 27 Page - Analog Devices

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Data Sheet
AD9577
Rev. 0 | Page 27 of 44
DETAILED BLOCK DIAGRAM
XTAL
OSC
REFCLK
XT1
XT2
MARGIN
SSCG
MAX_BW
REFSEL
CMOS
AD9577
DIVIDE
1 OR 2
SCL
SDA
I2C
CONTROL
22pF
22pF
VCO
2.15GHz
TO
2.55GHz
LDO1
DIVIDE BY
80 TO 131
FEEDBACK
DIVIDER
PLL1
NA
DIVIDE BY
2TO 6
DIVIDE BY
1TO 32
LVPECL/LVDS
REFOUT
OR 2 × CMOS
V0
D0
FORMAT1
DIVIDE BY
2TO 6
DIVIDE BY
1TO 32
LVPECL/LVDS
OR 2 × CMOS
V1
D1
VCO
DIVIDERS
OUTPUT
DIVIDERS
OUTPUT
BUFFERS
VCO
2.15GHz
TO
2.55GHz
LDO2
DIVIDE BY
80 TO 131
FEEDBACK
DIVIDER
PLL2
NB
DIVIDE BY
2TO 6
DIVIDE BY
1TO 32
LVPECL/LVDS
OR 2 × CMOS
V2
D2
FORMAT2
DIVIDE BY
2TO 6
DIVIDE BY
1TO 32
LVPECL/LVDS
OR 2 × CMOS
V3
D3
SDM
VCO
DIVIDERS
OUTPUT
DIVIDERS
OUTPUT
BUFFERS
3-BIT
0
1
FRAC
FRAC_TRIWAVE
SSCG
MOD
fPFD
CKDIV
FRAC
FRACSTEP
NUMSTEPS
SSCG
TRIWAVE
GENERATOR
FRAC_TRIWAVE
220nF
LDO
4× GND +
PADDLE
14× VS
Figure 32. Detailed Block Diagram



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