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AD9577BCPZ-R7 数据表(PDF) 12 Page - Analog Devices

部件名 AD9577BCPZ-R7
功能描述  Clock Generator with Dual PLLs
PDF  44 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9577BCPZ-R7 数据表(HTML) 12 Page - Analog Devices

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AD9577
Data Sheet
Rev. 0 | Page 12 of 44
TIMING CHARACTERISTICS
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL (see Figure 2)
Termination = 200 Ω to 0 V, ac-coupled to 50 Ω
oscilloscope; CLOAD = 5 pF
Output Rise Time, tRP
170
225
300
ps
20% to 80%, measured differentially
Output Fall Time, tFP
170
230
310
ps
80% to 20%, measured differentially
Skew
20
ps
Between the outputs of the same PLL at the
same frequency. SyncCh01/SyncCh23 set to 1
LVDS (see Figure 3)
Termination = 100 Ω differential; CLOAD = 5 pF
Output Rise Time, tRL
180
250
340
ps
20% to 80%, measured differentially
Output Fall Time, tFL
180
260
330
ps
80% to 20%, measured differentially
Skew
20
ps
Between the outputs of the same PLL at the
same frequency; SyncCh01/SyncCh23 set to 1
CMOS (see Figure 4)
Output Rise Time, tRC
250
680
950
ps
Termination is high impedance active probe,
total CLOAD = 5 pF, RLOAD = 20 kΩ, 20% to 80%
Output Fall Time, tFC
350
700
1000
ps
Termination is high impedance active probe,
total CLOAD = 5 pF, RLOAD = 20 kΩ, 80% to 20%
Skew
20
ps
Between the outputs of the same PLL at the
same frequency; SyncCh01/SyncCh23 set to 1
Timing Diagrams
DIFFERENTIAL
LVPECL
80%
50%
20%
tRP
VOD
tFP
Figure 2. LVPECL Timing, Differential
DIFFERENTIAL
LVDS
80%
50%
20%
tRL
VOD
tFL
Figure 3. LVDS Timing, Differential
SINGLE-ENDED
CMOS
80%
20%
tRC
tFC
Figure 4. CMOS Timing, Single-Ended, 5 pF Load



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