ADIS16228SLASHPCBZ datasheet(8/28 Pages) AD

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ADIS16228

Data Sheet

Rev. B | Page 8 of 28

BASIC OPERATION

The ADIS16228 uses a SPI for communication, which enables

a simple connection with a compatible, embedded processor

platform, as shown in Figure 8. The factory default configuration

for DIO1 provides a busy indicator signal that transitions low

when an event completes and data is available for user access.

Use the DIO_CTRL register (see Table 66) to reconfigure DIO1

and DIO2, if necessary.

SYSTEM

PROCESSOR

SPI MASTER

ADIS16228

SCLK

DIN

DOUT

SCLK

MOSI

MISO

3.3V

IRQ2

IRQ1

DIO2

VDD

I/O LINES ARE COMPATIBLE WITH

3.3V OR 5V LOGIC LEVELS

DIO1

Figure 8. Electrical Hook-Up Diagram

Table 6. Generic Master Processor Pin Names and Functions

Pin Name

Function

Slave select

SCLK

Serial clock

MOSI

Master output, slave input

MISO

Master input, slave output

IRQ1, IRQ2

Interrupt request inputs (optional)

The ADIS16228 SPI interface supports full duplex serial

communication (simultaneous transmit and receive) and uses

the bit sequence shown in Figure 12. Table 7 provides a list of

the most common settings that require attention to initialize

a processor serial port for the ADIS16228 SPI interface.

Table 7. Generic Master Processor SPI Settings

Processor Setting

Description

Master

The ADIS16228 operates as a slave.

SCLK Rate ≤ 2.5 MHz

Bit rate setting.

SPI Mode 3

Clock polarity/phase

(CPOL = 1, CPHA = 1).

MSB First

Bit sequence.

16-Bit

Shift register/data length.

Table 8 provides a list of user registers with their lower byte

addresses. Each register consists of two bytes that each has its own

unique 7-bit address. Figure 9 relates the bits of each register to

their upper and lower addresses.

UPPER BYTE

LOWER BYTE

Figure 9. Generic Register Bit Definitions

SPI WRITE COMMANDS

User control registers govern many internal operations. The

DIN bit sequence in Figure 12 provides the ability to write to

these registers, one byte at a time. Some configuration changes

and functions require only one write cycle. For example, set

GLOB_CMD[11] = 1 (DIN = 0xBF08) to start a manual capture

sequence. The manual capture starts immediately after the last bit

clocks into DIN (16th SCLK rising edge). Other configurations may

require writing to both bytes.

DIN

SCLK

Figure 10. SPI Sequence for Manual Capture Start (DIN = 0xBF08)

SPI READ COMMANDS

A single register read requires two 16-bit SPI cycles that also

use the bit assignments that are shown in Figure 12. The first

sequence sets R/W = 0 and communicates the target address

(Bits[A6:A0]). Bits[D7:D0] are don’t care bits for a read DIN

sequence. DOUT clocks out the requested register contents

during the second sequence. The second sequence can also use

DIN to set up the next read. Figure 11 provides a signal diagram

for all four SPI signals while reading the PROD_ID. In this

diagram, DIN = 0x5600 and DOUT reflects the decimal

equivalent of 16,228.

DOUT = 0011 1111 0110 0100 = 0x3F64 = 16,228 = PROD_ID

SCLK

DIN

DOUT

Figure 11. Example SPI Read, PROD_ID, Second Sequence

R/W

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

DB12

DB13

DB14

DB15

NOTES

1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).

SCLK

DIN

DOUT

DB13

DB14

DB15

Figure 12. Example SPI Read Sequence

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