ADP2325ACPZ-R7 datasheet(16/32 Pages) AD

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ADP2325

Data Sheet

Rev. 0 | Page 16 of 32

THEORY OF OPERATION

The ADP2325 is a full featured, dual output, step-down dc-to-dc

regulator based on a current mode architecture. It integrates two

high-side power MOSFETs and two low-side drivers for external

MOSFETs. The ADP2325 is designed for high performance

applications that require high efficiency and design flexibility.

The ADP2325 can operate with an input voltage from 4.5 V

to 20 V and can regulate the output voltage to as low as 0.6 V.

Additional features for flexible design include programmable

switching frequency, programmable soft start, external compen-

sation, independent enable inputs, and power-good outputs.

CONTROL SCHEME

The ADP2325 uses a fixed frequency, current mode PWM control

architecture during medium to full loads, but shifts to a power

save mode (PFM) at light loads when the PFM mode is enabled.

The power save mode reduces switching losses and boosts effi-

ciency under light loads.

When operating in the fixed frequency PWM mode, the duty

cycle of the integrated N-channel MOSFET (referred to inter-

changeably as NFET or MOSFET) is adjusted, this, in turn,

regulates the output voltage. When the device operates in

power save mode, the switching frequency is adjusted to regu

late the output voltage.

PWM MODE

In PWM mode, the ADP2325 operates at a fixed frequency

set by an external resistor. At the start of each oscillator cycle, the

high-side NFET turns on, placing a positive voltage across the

inductor. The inductor current increases until the current sense

signal crosses the peak inductor current threshold, turning off the

high-side NFET and turning on the low-side NFET (diode). This

places a negative voltage across the inductor, causing a reduction in

the inductor current. The low-side NFET (diode) stays on for the

remainder of the cycle or until the inductor current reaches zero.

PFM MODE

To enable the PFM mode, pull the MODE pin to ground. When

the COMPx voltage is below the PFM threshold voltage, the

device enters the PFM mode.

When the device enters the PFM mode, it monitors the FBx voltage

to regulate the output voltage. Because the high-side and low-

side NFETs are turned off, the load current discharges the output

capacitor causing the output voltage to drop. When the FBx

voltage drops below 0.605 V, the device starts switching and the

output voltage increases as the output capacitor is charged by the

inductor current. When the FBx voltage exceeds 0.62 V, the device

turns off both the high-side and low-side NFETs until the FBx

voltage drops to 0.605 V. In the PFM mode, the output voltage

ripple is larger than the ripple in the PWM mode.

PRECISION ENABLE/SHUTDOWN

The ADP2325 has two independent enable pins (EN1 and

EN2), one for each channel. The ENx pin has an internal pull-

down current source of 5 μA to provide a default turn-off whenever

an ENx pin is open.

When the voltage on the EN1 or EN2 pin exceeds 1.2 V (typical),

Channel 1 (per the EN1 pin) or Channel 2 (per the EN2 pin) is

enabled and the internal pull-down current source at the EN1

or EN2 pin is reduced to 1 μA, which allows the user to program

the UVLO lockout of the input voltage.

When the voltage on the EN1 or EN2 pin drops below 1.1 V

(typical), Channel 1 or Channel 2 turns off. When EN1 and

EN2 are both below 1.1 V, all of the internal circuits turn off

and the device enters the shutdown mode.

SEPARATE INPUT VOLTAGES

The ADP2325 supports two separate input voltages. This means

that the PVIN1 and PVIN2 voltages can be connected to two

different supply voltages. In these types of applications, because

the PVIN1 voltage provides the power supply for the internal regu-

lator and control circuitry, the PVIN1 voltage must be above the

UVLO voltage before the PVIN2 voltage begins to rise.

This feature allows for a cascading supply operation, as shown in

Figure 45 where PVIN2 is sourced from the Channel 1 output.

In this configuration, the Channel 1 output voltage needs to be high

enough to maintain Channel 2 in regulation, and the Channel 1

output voltage must be higher than the input voltage UVLO

threshold.

Figure 45. Cascading Supply Operation

INTERNAL REGULATOR (INTVCC)

The internal regulator provides a stable voltage supply for the

internal control circuits and a bias voltage for the low-side gate

drivers. It is recommended that a 1 μF ceramic capacitor be placed

between INTVCC and GND. The internal regulator also includes a

current-limit circuit for protection.

The internal regulator is active when either of the channels is

enabled. The PVIN1 pin provides power for the internal regulator,

which is used by both channels.

SW2

DL2

PVIN2

SW1

DL1

PGND

COUT1

PVIN1

ADP2325

VIN

VOUT1

VOUT2

COUT2

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