ADP2325ACPZ-R7 datasheet(22/32 Pages) AD

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ADP2325

Data Sheet

Rev. 0 | Page 22 of 32

LOW-SIDE POWER DEVICE SELECTION

The ADP2325 has integrated low-side MOSFET drivers, which

can drive the low-side N-channel MOSFETs (NFETs). The selec-

tion of the low-side N-channel MOSFET affects the dc-to-dc

regulator performance.

The selected MOSFET must meet the following requirements:

•

Drain source voltage (VDS) must be higher than 1.2 × VIN.

•

Drain current (ID) must be greater than 1.2 × ILIMIT_MAX, where

ILIMIT_MAX is the selected maximum current-limit threshold.

The ADP2325 low-side gate drive voltage is 5 V. Make sure that

the selected MOSFET can be fully turned on at 5 V.

Total gate charge (Qg at 5 V) must be less than 50 nC. Lower Qg

characteristics constitute higher efficiency.

When the high-side MOSFET is turned off, the low-side MOSFET

carries the inductor current. For low duty cycle applications, the

low-side MOSFET carries the current for most of the period. To

achieve higher efficiency, it is important to select a low on-resist-

ance MOSFET. The power conduction loss for the low-side

MOSFET can be calculated by

PFET_LOW = IOUT2 × RDSON × (1 − D)

where RDSON is the on resistance of the low-side MOSFET.

Make sure that the MOSFET can handle the thermal dissipation

due to the power loss.

In some cases, efficiency is not critical for the system; therefore,

the diode can be selected as the low-side power device. The

average current of the diode can be calculated by

IDIODE (AVG) = (1 − D) × IOUT

The reverse breakdown voltage rating of the diode must be

greater than the input voltage with an appropriate margin to

allow for ringing, which may be present at the SWx node. A

Schottky diode is recommended because it has a low forward

voltage drop and a fast switching speed.

If a diode is used for the low-side device, the ADP2325 must

enable the PFM mode by connecting the MODE pin to ground.

Table 10. Recommended MOSFETs

Vendor

Part No.

VDS

RDSON

Fairchild

FDS8880

30 V

10.7 A

12 mΩ

12 nC

Fairchild

FDMS7578

25 V

14 A

8 mΩ

8 nC

Fairchild

FDS6898A

20 V

9.4 A

14 mΩ

16 nC

Vishay

Si4804CDY

30 V

7.9 A

27 mΩ

7 nC

Vishay

SiA430DJ

20 V

10.8 A

18.5 mΩ

5.3 nC

AOS

AON7402

30 V

39 A

15 mΩ

7.1 nC

AOS

AO4884L

40 V

10 A

16 mΩ

13.6 nC

PROGRAMMING THE UVLO INPUT

The precision enable input can be used to program the UVLO

threshold and hysteresis of the input voltage, as shown in Figure 50.

Figure 50. Programming the UVLO Input

Use the following equation to calculate RTOP_EN and RBOT_EN:

μA

−

IN_FALLING

IN_RISING

TOP_EN

−

TOP

RISING

TOP

BOT

where:

VIN_RISING is the VIN rising threshold.

VIN_FALLING is the VIN falling threshold.

COMPENSATION COMPONENTS DESIGN

In peak current mode control, the power stage can be simplified

to a voltage controlled current source supplying current to the

output capacitor and load resistor. It is composed of one domain

pole and a zero contributed by the output capacitor ESR. The

control-to-output transfer function is shown in the following

equations:

























COMP

OUT

)

(

)

(

)

(

OUT

ESR

(

)

OUT

ESR

where:

AVI = 8.33 A/V.

R is the load resistance.

COUT is the output capacitance.

RESR is the equivalent series resistance of the output capacitor.

ENx

1.2V

EN CMP

4µA

1µA

PVINx

RTOP_EN

RBOT_EN

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