ADP2325ACPZ-R7 datasheet(17/32 Pages) AD

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Data Sheet

ADP2325

Rev. 0 | Page 17 of 32

BOOTSTRAP CIRCUITRY

The ADP2325 integrates the boot regulators to provide the gate

drive voltage for the high-side NFETs. The regulators generate

5 V bootstrap voltages between the BSTx and the SWx pins.

It is recommended that an X7R or X5R, 0.1 μF ceramic

capacitor be placed between the BSTx and the SWx pins.

LOW-SIDE DRIVER

The DLx pin provides the gate drive for the low-side N-channel

MOSFET. Internal circuitry monitors the gate driver signal to

ensure break-before-make switching to prevent crossconduction.

The VDRV pin provides the power supply to the low-side drivers.

It is limited to a 5.5 V maximum input; placing a 1 μF ceramic

capacitor close to this pin is recommended.

OSCILLATOR

A resistor from RT to GND programs the switching frequency

according to the following equation:

fSW [kHz] =

]

kΩ

[

000

OSC

A 200 kΩ resistor sets the frequency to 300 kHz, and a 100 kΩ

resistor sets the frequency to 600 kHz. Figure 46 shows the

typical relationship between fSW and ROSC.

Figure 46. fSW vs. ROSC

SYNCHRONIZATION

The SYNC pin can be configured as an input or an output by

setting the SCFG pin, as shown in Table 5.

Table 5. SCFG Configuration

SCFG

SYNC

Phase Shift

INTVCC

Output

0°

GND

Input

90°

180 kΩ to GND

Input

120°

100 kΩ to GND

Input

60°

When the SYNC pin is configured as an output, it generates a

clock with a frequency that is equal to the internal switching

frequency.

When the SYNC pin is configured as an input, the ADP2325 syn-

chronizes to the external clock that is applied to the SYNC pin, and

the internal clock must be programmed lower than the external

clock. The phase shift can be programmed by the SCFG pin.

When working in synchronization mode, the ADP2325 disables

the PFM mode and works only in the CCM mode.

SOFT START

Use the SSx pins to program the soft start time. Place a capacitor

between SSx and GND; an internal current charges this capacitor

to establish the soft start ramp. The soft start time can be calculated

using the following equation:





where:

CSS is the soft start capacitance.

ISS is the soft start pull-up current (3.5 μA).

If the output voltage is precharged prior to power-up, the ADP2325

prevents the low-side MOSFET from turning on until the soft

start voltage exceeds the voltage on the FBx pin.

During soft start, the ADP2325 uses frequency foldback to

prevent output current runaway. The switching frequency is

reduced according to the voltage present at the FBx pin, which

allows more time for the inductor to discharge. The correlation

between the switching frequency and the FBx pin voltage is listed

in Table 6.

Table 6. FBx Pin Voltage and Switching Frequency

FBx Pin Voltage

Switching Frequency

VFB ≥ 0.4 V

fSW

0.4 V > VFB ≥ 0.2 V

1/2 fSW

VFB < 0.2 V

1/4 fSW

PEAK CURRENT-LIMIT AND SHORT-CIRCUIT

PROTECTION

The ADP2325 uses a peak current-limit protection circuit to

prevent current runaway. Place a resistor between DLx and PGND

to program the peak current-limit value, as listed in Table 7.

The programmable peak current-limit threshold feature allows

for the use of a small size inductor for low current applications.

Table 7. Peak Current-Limit Threshold Setting

RILIM

Peak Current-Limit Threshold

Floating

8 A

47 kΩ

4.8 A

The ADP2325 uses hiccup mode for overcurrent protection.

When the peak inductor current reaches the current-limit

threshold, the high-side MOSFET turns off and the low-side

driver turns on until the next cycle while the overcurrent counter

is incremented.

200

300

400

600

800

500

700

900

1000

1100

1200

130

170

210

110

150

190

230

250

ROSC (kΩ)

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