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ADP2325ACPZ-R7 数据表(PDF) 25 Page - Analog Devices |
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ADP2325ACPZ-R7 数据表(HTML) 25 Page - Analog Devices |
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25 / 32 page ![]() Data Sheet ADP2325 Rev. 0 | Page 25 of 32 To meet the ±5% overshoot and undershoot requirement, use the following equation to calculate the capacitance: ( ) 2 2 _ 2 OUT OV OUT OUT STEP OV OUT_OV V V V L I K C − ∆ + × ∆ × = ( ) UV OUT OUT IN STEP UV OUT_UV V V V L I K C _ 2 2 ∆ × − × × ∆ × = For estimation purposes, use KOV = KUV = 2. For VOUT1 = 1.2 V, use COUT_OV1 = 188 µF and COUT_UV1 = 21 µF. For VOUT2 = 3.3 V, use COUT_OV2 = 55 µF and COUT_UV2 = 21 µF. For the 1.2 V rail, ESR of the output capacitor must be smaller than 8.3 mΩ, and the output capacitance must be larger than 188 µF. It is recommend that three 100 µF, X5R, 6.3 V ceramic capacitors be used, such as the GRM32ER60J107ME20 from Murata, with an ESR = 2 mΩ. For the 3.3 V rail, the ESR of the output capacitor must be smaller than 23 mΩ, and the output capacitance must be larger than 55 µF. It is recommended that two 47 µF, X5R, 6.3 V ceramic capacitors be used, such as the Murata GRM32ER60J476ME20, with an ESR = 2 mΩ. LOW-SIDE MOSFET SELECTION A low RDSON N-channel MOSFET is selected for high efficiency solutions. The MOSFET breakdown voltage must be greater than 1.2 V × VIN, and the drain current must be greater than 1.2 V × ILIMIT. It is recommended that a 30 V, N-channel MOSFET be used, such as the FDS8880 from Fairchild. The RDSON of the FDS8880 at a 4.5 V driver voltage is 12 mΩ, and the total gate charge is 12 nC. COMPENSATION COMPONENTS For better load transient and stability performance, set the cross frequency, fC, to fSW/10. In this case, fSW runs at 500 kHz; therefore, the fC is set to 50 kHz. For the 1.2 V rail, the 100 µF ceramic output capacitor has a derated value of 64 µF. kΩ 9 . 28 A/V 8.33 μS 500 V 0.6 kHz 50 μF 64 3 V 2 . 1 2 = × × × × × × × = π C1 R ( ) pF 1598 kΩ 9 . 28 μF 64 3 Ω 001 . 0 Ω 24 . 0 = × × + = C1 C pF 6 . 6 kΩ 9 . 28 μF 64 3 Ω 001 . 0 = × × = CP1 C By choosing standard components where RC1 = 28 kΩ and CC1 = 1500 pF, no CCP1 is needed. Figure 52 shows the 1.2 V rail bode plot at 5 A. The cross frequency is 42 kHz and the phase margin is 50°. Figure 52. Bode Plot for 1.2 V Rail For the 3.3 V rail, the 47 µF ceramic output capacitor has a derated value of 32 µF. kΩ 5 . 26 A/V 8.33 μS 500 V 0.6 kHz 50 μF 2 3 2 V 3 . 3 2 = × × × × × × × = π C2 R ( ) pF 1594 kΩ 5 . 26 μF 32 2 Ω 001 . 0 Ω 66 . 0 = × × + = C2 C pF 4 . 2 kΩ 5 . 26 μF 32 2 Ω 001 . 0 = × × = CP2 C By using standard component values of RC2 = 27 kΩ and CC2 = 1500 pF, no CCP2 is needed. Figure 53 shows the 3.3 V rail bode plot at 5 A. The cross frequency is 55 kHz and phase margin is 67°. Figure 53. Bode Plot for 3.3 V Rail 1k –60 60 –48 48 –36 –24 –12 12 24 36 FREQUENCY (Hz) 0 –180 180 –144 144 –108 –72 –36 36 72 108 0 10k 100k 1 2 1M 1k –60 60 –48 48 –36 –24 –12 12 24 36 FREQUENCY (Hz) 0 –180 180 –144 144 –108 –72 –36 36 72 108 0 10k 100k 1 2 1M |
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