SP7800ADS/02

SP7800A 12-Bit 3

µs Sampling A/D Converter

© Copyright 2000 Sipex Corporation

8

maximum system accuracy, both should be well–

isolated from digital supplies with wide load varia-

tions.

To limit the effects of digital switching elsewhere in a

system on the analog performance of the system, it

often makes sense to run a separate +5V supply

conductor from the supply regulator to any analog

components requiring +5V, including the SP7800A.

If the SP7800Atraces cannot be separated back to the

power supply terminals, and therefore share the same

trace as the logic supply currents, then a 10 Ohm

isolating resistor should be used between the board

supply and pin 24 (V

keep V

be connected together and bypassed with a parallel

combination of a 6.8

µF Tantalum capacitor and a

0.1

µFceramiccapacitorlocatedclosetotheconverter

to obtain noise-free operation. (See Figure 1). Noise

on the power supply lines can degrade converter

performance, especially noise and spikes from a

switching power supply. Appropriate supplies or

filters must be used.

TheGNDpins(4and13)arealsoseparatedinternally,

and should be directly connected to a ground plane

undertheconverter.Agroundplaneisusuallythebest

solution for preserving dynamic performance and

reducing noise coupling into sensitive converter cir-

cuits. Where any compromises must be made, the

common return of the analog input signal should be

referenced to pin 4, AGND, on the SP7800A, which

prevents any voltage drops that might occur in the

power supply common returns from appearing in

series with the input signal.

Couplingbetweenanaloginputanddigitallinesshould

be minimized by careful layout. For instance, if the

lines must cross, they should do so at right angles.

Parallel analog and digital lines should be separated

from each other by a pattern connected to common.

If external full scale and offset potentiometers are

used, the potentiometers and related resistors should

be located as close to the SP7800A as possible.

“Hot Socket” Precaution

Two separate +5V V

minimize noise caused by digital transients. If one pin

is powered and the other is not, the SP7800A may

drawexcessivecurrent.Innormaloperation,thisisnot

aproblembecausebothpinswillbesolderedtogether.

However, during evaluation, incoming inspection,

repair, etc., where the potential of a “Hot Socket”

exists, care should be taken to apply power to the

SP7800A only after it has been socketed.

Minimizing “Glitches”

Coupling of external transients into an analog-to-

digitalconvertercancauseerrorswhicharedifficultto

debug. In addition to the discussions earlier on layout

considerationsforsupplies,bypassingandgrounding,

there are several other useful steps that can be taken to

get the best analog performance out of a system using

Figure 4. Acquisition and Conversion Timing

R/C

BUSY

Converter

Mode

Acquisition

Conversion

Acquisition

Conversion

Hold Time

SYMBOL/PARAMETER

MIN

TYP

MAX

UNITS

t

DBC

BUSY delay from R/C

80

150

ns

t

B

BUSY Low

2.5

2.7

µs

t

AP

Aperture Delay

13

ns

∆t

AP

Aperture Jitter

150

ps, rms

t

C

Conversion Time

2.47

2.70

µs