SP7800ADS/02

SP7800A 12-Bit 3

µs Sampling A/D Converter

© Copyright 2000 Sipex Corporation

10

SYMBOL/PARAMETER

MIN

TYP

MAX

UNITS

t

W

R/C Pulse Width

40

10

ns

t

DBC

BUSY delay from R/C

80

150

ns

t

B

BUSY LOW

2.47

2.7

µs

t

AP

Aperture Delay

13

ns

∆t

AP

Aperture Jitter

150

ps, rms

t

C

Conversion Time

2.5

2.70

µs

t

DBE

BUSY from End of Conversion

100

ns

t

DB

BUSY Delay after Data Valid

25

75

200

ns

t

A

Acquisition Time

130

300

ns

t

Throughput Time

3.0

µs

t

HDR

Valid Data Held After R/C LOW

20

50

ns

t

S

CS or HBE LOW before R/C Falls

25

5

ns

t

H

CS or HBE LOW after R/C Falls

25

0

ns

t

DD

Data Valid from CS LOW, R/C HIGH, and HBE

65

150

ns

in Desired State (Load = 100pF)

t

HL

Delay to Hi-Z State after R/C Falls or

50

150

ns

CS Rises (3K

Ω Pullup or Pulldown

All parameters Guaranteed By Design

AC DYNAMIC TIMING DATA

Figure 7. Conversion Start Timing

R/C

BUSY

Data

BUS

CS or

HBE

Data Valid

Hi-Z State

tions, the multiplexer can be switched as soon as R/C

goes LOW (with appropriate delays), but this may

affect the conversion if the switched signal shows

glitches or significant ringing at the SP7800A input.

Whenever possible, it is safer to wait until the conver-

sion is completed before switching and multiplexer.

The extremely fast acquisition time and conversion

time of the SP7800A make this practical in many

applications.

Naturally, transients on the analog input signal are to

be avoided, especially at times within

±20ns of R/C

going LOW, when they may be trapped as part of the

charge on the capacitor array. This requires careful

layout of the circuit in front of the SP7800A.

Finally, in multiplexed systems, the timing relative to

when the multiplexer is switched may affect the

analog performance of the system. In most applica-