SP7800ADS/02

SP7800A 12-Bit 3

µs Sampling A/D Converter

© Copyright 2000 Sipex Corporation

6

CS

R/C

HBE

BUSY

OPERATION

1

X

X

1

None – outputs in Hi-Z state.

01

0

0

1

Holds signal and initiates conversion.

0101

Output three-state buffers enabled once

conversion has finished.

0111

Enable hi-byte in 8-bit bus mode.

01

0

1

1

Inhibit start of conversion.

0011

None – outputs in Hi-Z state.

X

X

X

0

Conversion in progress. Outputs Hi-Z

state. New conversion inhibited until

present conversion has finished.

Table 1. Control Line Functions

onR/C.Thethree-statedataoutputbuffersareenabled

when R/C is HIGH and BUSY is HIGH. Thus, there

are two possible modes of operation: conversion can

be initiated with either positive or negative pulses. In

either case, the R/C pulse must remain LOW a

minimum of 40ns.

Figure 5 illustrates timing when conversion is initi-

ated by an R/C pulse which goes LOW and returns

HIGH during the conversion. In this case (Convert

Mode),thethree-stateoutputsgointotheHi-Zstatein

responsetothefallingedgeofR/C,andareenabledfor

external access to the data after completion of the

conversion.

Figure 6 illustrates the timing when conversion is

initiated by a positive R/C pulse. In this mode (Read

Mode), the output data from the previous conversion

is enabled during the HIGH portion of R/C. A new

conversion starts on the falling edge of R/C, and the

three-stateoutputsreturntotheHi-Zstateuntilthenext

occurrence of a HIGH on R/C.

Conversion Start

A conversion is initiated on the SP7800A only by a

negative transition occurring on R/C, as shown in

Table 2. No other combination of states or transitions

will initiate a conversion. Conversion is inhibited if

either CS or HBE are HIGH, or if BUSY is LOW. CS

andHBEshouldbestableaminimumof25nspriorto

the transition on R/C. Timing relationships for start of

conversion are illustrated in Figure 7.

The BUSY output indicates the current state of the

converter by being LOW only during conversion.

During this time the three-state output buffers remain

in a Hi-Z state, and therefore data cannot be read

during conversion. During this period, additional

transitions on the three digital inputs (CS, R/C and

HBE) will be ignored, so that conversion cannot be

prematurely terminated or restarted.

Internal Clock

The SP7800A has an internal clock that is factory

trimmed to achieve a typical conversion time of

2.6

µs, and a maximum conversion time over the

full operating temperature range of 2.7

µs. No

external adjustments are required, and with the

guaranteed maximum acquisition time of 300ns,

throughput performance is assured with convert

pulses as close as 3

µs.

Reading Data

Afterconversionisinitiated,theoutputbuffersremain

in a Hi-Z state until the following three logic condi-

tions are simultaneously met: R/C is HIGH, BUSY is

HIGH and CS is LOW. Upon satisfying these condi-

tions, the data lines are enabled according to the state

of HBE. See Figure 7 for timing relationships and

specifications.

CALIBRATION...

Optional External Gain And Offset Trim

Offset and full-scale errors may be trimmed to zero

using external offset and full-scale trim potenti-

ometers connected to the SP7800A as shown in

Figure 3.

If adjustment of offset and full scale is not required,

connections as shown in Figure 2 should be used.

Calibration Procedure

Applyaprecisioninputvoltagesourcetoyourchosen

input range (

±10V range at pin1 or ±5V at pin 2). Set

the A/D to convert continuously. Monitor the output

code.Trimtheoffsetfirst,thengain.Usetheappropri-

ate input voltages and output target codes for your

chosen input range as follows. The recommended

offset calibration voltage values eliminate interaction

between the offset and gain calibration.

Figure 2. a)

±10V Range b) ±5V Range — Without Trims

1

2

±10V

Input

SP7800A

1

2

±5V

Input

SP7800A