SP7800ADS/02

SP7800A 12-Bit 3

µs Sampling A/D Converter

© Copyright 2000 Sipex Corporation

3

SPECIFICATIONS (continued)

T

PARAMETER

MIN .

TYP.

MAX .

UNITS

CONDITIONS

AC ACCURACY

T

Signal to (Noise + Distortion) Ratio

f

–J

67

70

dB

–K

69

71.0

dB

Signal to Noise Ratio (SNR)

f

–J

68

71

dB

–K

70

71.5

dB

SAMPLING DYNAMICS

Aperture Delay

13

ns

Aperture Jitter

150

ps, rms

Transient Response

Note 5

–J

130

ns

–K

150

ns

Overvoltage Recovery

150

ns

Note 6

DIGITAL INPUTS

T

Logic Levels

V

IL

–0.3

+0.8

V

V

IH

+2.4

+5.3

V

I

IL

–5

µA

I

IH

+5

µA

DIGITAL OUTPUTS

Data Format

Parallel; 12-bit or 8-bit/4-bit

Data Coding

Binary; Offset Binary

V

OL

DGND

+0.4

V

I

V

OH

+2.4

V

DD

VI

I

±0.1

±5

µA

POWER SUPPLY REQUIREMENTS

Rated Voltage

+4.75

+5.0

+5.25

V

V

Current

18

21

mA

I

S

Power Consumption

90

mW

ENVIRONMENTAL AND MECHANICAL

Specification

–J, –K

0

+70

°C

Storage

–65

+150

°C

Package

–_N

24–pin Narrow DIP

–_S

24–pin SOIC

NOTES

1.

Adjustable to zero with external potentiometer.

2.

LSB means Least Significant Bit. For SP7800A, 1LSB = 2.44mV for

±5V range, 1 LSB = 4.88mV for

±10V range.

3.

Measured at mid-range, between 4.75 < V

4.

All specifications in dB are referred to a full-scale input, either

±10V or ±5V.

5.

For full-scale step input, 12-bit accuracy attained in specified time.

6.

Recovers to specified performance in specified time after 2 x F