SP7800ADS/02

SP7800A 12-Bit 3

µs Sampling A/D Converter

© Copyright 2000 Sipex Corporation

9

R/C

BUSY

Converter

Mode

Data

BUS

Acquire

Convert

Acquire

Convert

Data Valid

Hi-Z State

Hi-Z State

Data Valid

t

W

t

B

Figure 5. Convert Mode Timing — R/C Pulse LOW, Outputs Enabled After Conversion

theSP7800A.Thesepotentialsystemproblemsources

are particularly important to consider when develop-

ing a new system, and looking for the causes of errors

in breadboards.

First, care should be taken to avoid glitches during

critical times in the sampling and conversion process.

SincetheSP7800Ahasan internal sample/hold func-

tion,thesignalthatputsitintotheholdstate(R/Cgoing

LOW) is critical, as it would be on any sample/hold

amplifier. The R/C falling edge should be sharp (5 to

10ns), have low jitter and minimal ringing, especially

during the 20ns after it falls.

Although not normally required, it is also good prac-

tice to avoid glitches from coupling to the SP7800A

while bit decisions are being made. Since the above

discussion calls for a fast, clean rise and fall on R/C, it

makes sense to keep the rising edge of the convert

pulse outside the time when bit decisions are being

made. In other words, the convert pulse should either

be short (under 100ns so that it transitions before the

MSB decision), or relatively long (over 2.75

µs to

transition after the LSB decision).

Next, although the data outputs are forced into a Hi-Z

state during conversion, fast bus transients can still be

capacitivelycoupledintotheSP7800A.Ifthedatabus

experiences fast transients during conversion, these

transientscanbeattenuatedbyaddingalogicbufferto

the data outputs. The BUSY output can be used to

enable the buffer.

Figure 6. Read Mode Timing — R/C Pulse HIGH, Outputs Enabled Only When R/C is High

R/C

BUSY

Converter

Mode

Data

BUS

Acquire

Convert

Acquire

Convert

Data

Valid

Hi-Z State

Hi-Z State

t

W

t

B

Data

Valid

Hi-Z State