TNETX4090GGP datasheet(57/78 Pages) TI1

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TNETX4090

ThunderSWITCH II™ 9-PORT 100-/1000-MBIT/S ETHERNET™ SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

other flow-control mechanisms

hardware flow control

If a port were in MII or GMII mode and full duplex, normally, its Mxx_COL would not be needed. Hardware flow

control has been added by preventing the start of a frame transmission if the Mxx_COL is high. This is useful

in ring mode; the Mxx_COL can be tied to the FLOW of the upstream neighbor for hardware flow control.

multicast limit

Because buffer resources for multicast (or broadcast) frames are released only when the last port has

transmitted the frame, multicast packets to fast and slow ports are released at the slow-port rate. Multicast traffic

from a fast port to a slow port could cause back pressure to be applied to the source port, blocking input from

that port. This occurs even if at least one of the ports in the multicast could have kept pace with the inbound

multicast packets. The MCastLimit register can limit the number of multicast packets allowed to be pending at

any output port. When the limit is reached, that port is not added to the routing vector of the next multicast packet

for which it was eligible. Eligibility is restored when the number of backlogged packets is again below the limit.

MCastLimit allows the user to set the ports subject to this restriction, and set the limit in 8 binary steps, from

2 to 256. The spanning-tree BPDU multicast packet is exempt from this limit.

other behavior changes resulting from flow-control bits or terminals

Clearing (the default) holbrm in the RingPorts register includes the test for buffer use controlled by the holb bit

in SysControl into the action of the FLOW terminal. FLOW goes high if either the number of buffers left is less

than the FlowThreshold value or a ring-mode port receive operation has exceeded its fair share of buffers.

Setting holbrm = 1 makes FLOW respond only to FlowThreshold value violations.

system test capabilities

RDRAM

The external RDRAM can be read and written using regular DIO accesses following a stop. Individual bytes can

be read and written. However, as the RDRAM memory is actually accessed in 128-byte pages, performing

128-byte accesses is the most efficient.

To access the RDRAM, the TNETX4090 must not be operating. The user must perform a reset and not set start

in SysControl. Both start and initd in SysControl must be 0. In addition, rdinit in SysTest must be set, indicating

that the RDRAM has initialized. This initialization sequence occurs automatically after a hard reset.

Read or write accesses to RDRAM are invoked via rdram and rdwrite in SysTest. Setting rdram to 1 causes a

128-byte transfer between the device and the RDRAM memory to be initiated.

D The transfer direction is determined by rdwrite.

D The external memory byte address for the access is specified by ramaddress in RAMAddress.

D Data to be read from or written to RDRAM is accessed indirectly via RAMData.

writing RDRAM

Writing to RDRAM memory is accomplished as follows:

Write the byte address for the access to ramaddress in RAMAddress.

Write the data for the access to RAMData. Up to 64 bytes can be written, if all but the six least significant

bits of the address are the same for all the data. Inc in RAMAddress can be used to autoincrement the

address.

Set rdwrite = 0 and rdram = 1 (these can be written simultaneously).

If required, poll rdram until it becomes 0. This indicates that the write has completed.

TNETX4090GGP 数据表(PDF) 57 Page - Texas Instruments

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