TNETX4090GGP datasheet(64/78 Pages) TI1

64 / 78 page

TNETX4090

ThunderSWITCH II™ 9-PORT 100-/1000-MBIT/S ETHERNET™ SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

GMII (port 8)

Figures 18–20 show the timing for the 100-/1000-Mbit/s GMII when operating at 1000 Mbit/s.

Both Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD7–MxxRXD0 is driven by the

PHY on the falling edge of Mxx_RCLK. Mxx_RXD7–MxxRXD0 timing must be met during clock periods in which

Mxx_RXDV is asserted. Mxx_RXDV is asserted and deasserted by the PHY on the falling edge of Mxx_RCLK.

Mxx_RXER is driven by the PHY on the falling edge of Mxx_RCLK.

GMII receive (see Figure 18)

NO.

MIN

MAX

UNIT

tsu(Mxx_RXD)

Setup time, Mxx_RXD7–Mxx_RXD0 valid before Mxx_RCLK

↑

tsu(Mxx_RXDV) Setup time, Mxx_RXDV valid before Mxx_RCLK↑

tsu(Mxx_RXER) Setup time, Mxx_RXER valid before Mxx_RCLK↑

th(Mxx_RXD)

Hold time, Mxx_RXD7–Mxx_RXD0 valid after Mxx_RCLK

↑

th(Mxx_RXDV)

Hold time, Mxx_RXDV valid after Mxx_RCLK

↑

th(Mxx_RXER)

Hold time, Mxx_RXER valid after Mxx_RCLK

↑

Mxx_RXD7–Mxx_RXD0

Mxx_RXDV

Mxx_RXER

Mxx_RCLK

Figure 18. GMII Receive

Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_GTCLK is derived directly from

Mxx_RFCLK. Mxx_TXD7–Mxx_TXD7 is driven by the reconciliation sublayer synchronous to the Mxx_GTCLK.

Mxx_TXEN is asserted and deasserted by the reconciliation sublayer synchronous to the Mxx_GTCLK rising

edge. Mxx_TXER is driven synchronous to the rising edge of Mxx_GTCLK.

GMII transmit (see Figure 19)

NO.

MIN

MAX

UNIT

td(Mxx_TXD)

Delay time, from Mxx_GTCLK

↑ to Mxx_TXD3–MxxTXD0 valid

1.5

4.5

td(Mxx_TXEN)

Delay time, from Mxx_GTCLK

↑ to Mxx_TXEN valid

1.5

4.5

td(Mxx_TXER)

Delay time, from Mxx_GTCLK

↑ to Mxx_TXER valid

1.5

4.5

Mxx_TXD7–Mxx_TXD0

Mxx_TXEN

Mxx_TXER

Mxx_GTCLK

Figure 19. GMII Transmit

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