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TNETX4090GGP 数据表(PDF) 69 Page - Texas Instruments

部件名 TNETX4090GGP
功能描述  ThunderSWITCH IIE 9-PORT 100-/1000-MBIT/S ETHERNETE SWITCH
PDF  78 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETX4090GGP 数据表(HTML) 69 Page - Texas Instruments

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TNETX4090
ThunderSWITCH II™ 9-PORT 100-/1000-MBIT/S ETHERNET™ SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
69
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
DIO interface
The DIO interface is simple and asynchronous to allow easy adaptation to a range of microprocessor devices
and computer system interfaces.
DIO and DMA writes (see Figure 25)
NO.
MIN
MAX
UNIT
1
tw(SCS)
Pulse duration, SCS
↓
2tc
ns
2
tsu(SRNW)
Setup time, SRNW valid before SCS
↓
0
ns
3
tsu(SAD)
Setup time, SAD1–SAD0, SDMA valid before SCS
↓
0
ns
4
tsu(SDATA)
Setup time, SAD7–SAD0 valid before SCS
↓
0
ns
5
th(SRNW)
Hold time, SRNW low after SRDY
↓
0
ns
6
th(SAD)
Hold time, SAD1–SAD0, SDMA valid after SRDY
↓
0
ns
7
th(SDATA)
Hold time, SAD7–SAD0 valid after SRDY
↓
0
ns
8
th(SCSL)
Hold time, SCS low after SRDY
↓
0
ns
9
td(SRDYZH) Delay time from SCS↓ to SRDY↑
10
ns
10
td(SRDYHL)
Delay time from SCS
↓ to SRDY↓
2tc
†
ns
11
td(SRDYLH)
Delay time from SCS
↑ to SRDY↑
tc
2tc+10
ns
12
th(SCSH)
Hold time, SCS high after SRDY
↑
0
ns
13
tw(SRDY)
Pulse duration, SRDY
↑
tc
ns
14
td(SINT)
Delay time from SRDY
↓ to SINT valid. (write to INT or INT_Enable register)
2tc
ns
† When the switch is performing certain internal operations (e.g., EEPROM load), there is a delay of up to 20 ms (24C02) or 800 ms (24C08)
between SCS being asserted and SRDY being asserted.
SCS
8
11
12
1
2
9
3
4
10
5
6
7
13
SRNW
SAD1–SAD0
SDMA
SDATA7–
SDATA0
SRDY
14
SINT
Figure 25. DIO and DMA Writes



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