TNETA1585PCM datasheet(21/32 Pages) TI1

部件名	TNETA1585PCM

功能描述	ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES

PDF	32 Pages

Scroll/Zoom	100%

制造商	TI1 [Texas Instruments]

网页	http://www.ti.com

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TNETA1585

ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE

WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES

SDNS041A – NOVEMBER 1996 – REVISED JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

operating characteristics over recommended operating conditions (see Figure 4)

parameter-memory interface – write operation

NO.

PARAMETER

MIN

MAX

UNIT

td(PMAD)

Delay time, from CLOCK

↑ to PMAD15–PMAD0 valid

td(PMDATA)

Delay time, from CLOCK

↑ to PMDATA31–PMDATA0 valid

td(PMOE)

Delay time, from CLOCK

↑ to PMOE↑

td(PMWE)1

Delay time, from CLOCK

↓ to PMWE↓

td(PMWE)2

Delay time, from CLOCK

↓ to PMWE↑

PMAD15–

PMAD0

(output)

PMOE

(output)

PMWE

(output)

PMDATA31–

PMDATA0

(output)

Valid

CLOCK

(input)

Valid

Figure 4. Parameter-Memory Interface – Write Operation

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