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TNETA1585PCM 数据表(PDF) 26 Page - Texas Instruments |
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TNETA1585PCM 数据表(HTML) 26 Page - Texas Instruments |
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26 / 32 page  TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES SDNS041A – NOVEMBER 1996 – REVISED JULY 1998 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements (see Figure 9) slave interface – write operation NO. MIN MAX UNIT 1 tsu(SCAD) Setup time, SCAD5–SCAD0 valid before CLOCK ↑ 7 ns 2 tsu(SCDATA) Setup time, SCDATA31–SCDATA0 valid before CLOCK ↓ 0 ns 3 tsu(SCWE) Setup time, SCWE low before CLOCK ↑ 5 ns 4 tsu(SCSEL) Setup time, SCSEL low before CLOCK ↑ 5 ns 5 tsu(SCOE) Setup time, SCOE high before CLOCK ↓ 5 ns 6 th(SCAD) Hold time, SCAD5–SCAD0 valid after CLOCK ↑ 0 ns 7 th(SCDATA) Hold time, SCDATA31–SCDATA0 valid after CLOCK ↓ 7 ns 8 th(SCWE) Hold time, SCWE low after CLOCK ↑ 4 ns 9 th(SCSEL) Hold time, SCSEL low after CLOCK ↑ 0 ns 10 th(SCOE) Hold time, SCOE high after CLOCK ↓ 2 ns SCDATA31– SCDATA0 (input) SCOE (input) SCSEL (input) Valid SCAD5– SCAD0 (input) Valid CLOCK (input) 1 SCWE (input) 4 3 6 8 7 2 9 5 10 Figure 9. Slave Interface – Write Operation |
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