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TNETA1585PCM 数据表(PDF) 7 Page - Texas Instruments |
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TNETA1585PCM 数据表(HTML) 7 Page - Texas Instruments |
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7 / 32 page ![]() TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES SDNS041A – NOVEMBER 1996 – REVISED JULY 1998 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detail description The TNETA1585 device contains the following interfaces: • COPI interface: Slave-control interface Coprocessor interface • Receive-UTOPIA interface • Parameter-memory interface • JTAG interface COPI interface The traffic-coprocessor interface (COPI) provides the means of communication between the TNETA1585 and the master device. It consists of the slave interface and the coprocessor interface. slave-control interface The slave-control (SC) interface consists of a 32-bit data bus, a 6-bit address bus, an output-enable terminal (SCOE), a write-enable terminal (SCWE), and a select terminal (SCSEL). When used with the TNETA1575 SAR device, the TNETA1585 slave-control interface is mapped into the SAR’s control-memory space starting at address 10000h and extending to address 1FFFFh. This equates to a total address space of 64K 32-bit words with 64 locations applicable to the TNETA1585. The TNETA1575 uses its select terminal to choose between its control memory and the TNETA1585. The TNETA1585 is a slave to all to-and-from transfers. These are initiated by the master device that is a SAR or switch port controller. Table 1 lists the slave registers that are directly accessible through the slave interface. A heading specifies the slave-interface addresses as control-memory addresses because of the TNETA1575 mapping of the TNETA1585. Each register is either host associated or SAR associated. The host accesses the host-associated registers through the SAR and are used by the host to initialize the TNETA1585 and to configure the TNETA1585’s other internal-data structures and associated parameter memory. The host has access to the TNETA1585’s other internal-data structures and associated parameter memory through the host-associated read address, read data, write address, and write data registers as described in the TNETA1585 Programmer’s Reference Guide, literature number SDNU016. The SAR-associated registers are used by the SAR to obtain information related to the scheduling of cells. The next-cell register indicates when one of the TNETA1585 scheduled connections is ready to transmit and what type of cell to transmit. It also provides information on how to build the associated cell’s header. In addition, if the SAR is instructed by the TNETA1585 to transmit an RM cell for ABR connections, the SAR obtains the properly formatted RM-cell payload from one of the RM-cell-contents FIFOs of the TNETA1585. |
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