TNETA1585PCM datasheet(4/32 Pages) TI1

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TNETA1585

ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE

WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES

SDNS041A – NOVEMBER 1996 – REVISED JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

slave interface

TERMINAL

RESET

NAME

NO.

PGF

NO.

PCM

I/O

RESET

STATE

DESCRIPTION

SCAD5 SCAD0

33–36

29–32

I (TTL)

Slave control address SCAD5 SCAD0 consists of a 6 bit address

SCAD5–SCAD0

38–39

34–35

I (TTL)

Slave-control address. SCAD5–SCAD0 consists of a 6-bit address.

43–45

39 41

47–49

39–41

43–45

51–53

55 56

43 45

47–49

55–56

59–60

51–52

54 56

SCDATA31–

59 60

54–56

58 60

I/O

(TTL/

Hi Z

Slave control data SCDATA31 SCDATA0 consists of 32 bit data

SCDATA31

SCDATA0

64–66

58–60

62–64

(TTL/

CMOS)

Hi-Z

Slave-control data. SCDATA31–SCDATA0 consists of 32-bit data.

68–70

73 75

62 64

66–68

CMOS)

73–75

78–79

70–71

73 75

78 79

81–83

73–75

77 80

85–88

77–80

SCOE

I (TTL)

Slave-control output enable. SCOE is active low. When SCOE and SCSEL are

low, TNETA1585 reads are enabled.

SCSEL

I (TTL)

Slave-control select. SCSEL is active low. SCSEL enables the slave-control

interface.

SCWE

I (TTL)

Slave-control write enable. SCWE is active low. When SCWE and SCSEL are

low, TNETA1585 writes are enabled.

coprocessor interface

TERMINAL

RESET

NAME

NO.

PGF

NO.

PCM

I/O

RESET

STATE

DESCRIPTION

CLOCK

I (TTL)

Clock. The RCCX, TCCX, and DAX inputs are clocked into the device on the

rising edge of the clock input. This clock also is used as an operating clock

source for the TNETA1585.

COPFULL

(CMOS)

Low

Receive-FIFO full indication. COPFULL provides an indication of the status of

the receive UTOPIA interface FIFO. When the PHY/ATM input is low, COPFULL

goes high when the receive UTOPIA interface FIFO is full. When the PHY/ATM

input is high, COPFULL goes high when the FIFO is within 4 bytes of being full.

DAX

I (TTL)

Data-availability indication. DAX provides an indication to the device when data

is available on a particular channel or when the SAR has completed

segmentation of queued packets.

INTR

(CMOS)

High

Local interrupt. INTR provides an interrupt indication from the traffic

coprocessor to the SAR.

RCCX

I (TTL)

Receive-cell status indication. RCCX provides an indication to the device that

a cell has been received on the UTOPIA interface along with the receive channel

number assigned to the cell.

RESET

I (TTL)

Reset. When low, RESET resets the device.

TCCX

I (TTL)

Transmit-cell status indication. TCCX provides an indication to the device that

a cell has been transmitted from the SAR along with the channel number of that

cell.

TNETA1585PCM 数据表(PDF) 4 Page - Texas Instruments

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TNETA1585PCM 数据表(PDF) 4 Page - Texas Instruments

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