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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SPIRIT1 数据表(PDF) 67 Page - STMicroelectronics |
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SPIRIT1 数据表(HTML) 67 Page - STMicroelectronics |
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67 / 94 page  SPIRIT1 MCU interface Doc ID 022758 Rev 3 67/94 Figure 12. SPI “read” operation Figure 13. SPI “command” operation Concerning the first byte, the MSB is an A/C bit (Address/Commands: 0 indicates that the following byte is an address, 1 indicates that the following byte is a command code), while the LSB is a W/R bit (Write/Read: 1 indicates a read operation). All other bits must be zero. Read and write operations are persistently executed while CSn is kept active (low), the address being automatically incremented (burst mode). Accessing the FIFO is done as usual with the read and write commands, by putting, as the address, the code 0xFF. Burst mode is available to access the sequence of bytes in the FIFO. Clearly, RX-FIFO is accessed with a read operation, TX-FIFO with a write operation. Details of the SPI parameters are reported below. Table 31. SPI interface timing requirements Symbol Parameter Min. Max. Unit fSCLK SCLK frequency 10 MHz tsp CSn low to positive edge on SCLK 2 µs |
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