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WM8945ECS/R 数据表(PDF) 66 Page - Wolfson Microelectronics plc |
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WM8945ECS/R 数据表(HTML) 66 Page - Wolfson Microelectronics plc |
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66 / 169 page  WM8945 Production Data w PD, May 2011, Rev 4.1 66 AUDIO DATA FORMATS Three basic audio data formats are supported: Left justified I 2S DSP mode All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information. PCM operation is supported using the DSP mode. The WM8945 is a mono device. By default, the WM8945 transmits ADCs data on the Left channel only of the Digital Audio Interface, and receives DAC data on the Left channel. The ADC transmit configuration can be set using the ADCR_SRC and ADCL_SRC bits; the DAC receive channel can be selected using the DACL_SRC bit. Digital inversion of the ADC and DAC data is also possible. The register bits controlling audio data format and channel configuration are described in Table 44. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4 (04h) Audio Interface 9 ADCR_SRC 1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = No data is output on right channel 8 ADCL_SRC 0 Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = No data is output on left channel 6 DACL_SRC 0 Left DAC Data Source Select 0 = Left DAC outputs left interface data 1 = Left DAC outputs right interface data 5 BCLK_INV 0 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted 4 LRCLK_INV 0 LRCLK Polarity / DSP Mode A-B select. Right, left and I 2S modes – LRCLK polarity 0 = Not Inverted 1 = Inverted DSP Mode – Mode A-B select 0 = MSB is available on 2 nd BCLK rising edge after LRCLK rising edge (mode A) 1 = MSB is available on 1 st BCLK rising edge after LRCLK rising edge (mode B) 3:2 WL [1:0] 10 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Note – see “Companding” for the selection of 8-bit mode. |
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