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WM8945ECS/R 数据表(PDF) 68 Page - Wolfson Microelectronics plc |
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WM8945ECS/R 数据表(HTML) 68 Page - Wolfson Microelectronics plc |
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68 / 169 page ![]() WM8945 Production Data w PD, May 2011, Rev 4.1 68 In device master mode, the LRCLK output resembles the frame pulse shown in Figure 24 and Figure 25. In device slave mode, Figure 26 and Figure 27, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. Figure 24 DSP/PCM Mode Audio Interface (mode A, LRCLK_INV=0, Master) Figure 25 DSP/PCM Mode Audio Interface (mode B, LRCLK_INV=1, Master) Figure 26 DSP/PCM Mode Audio Interface (mode A, LRCLK_INV=0, Slave) |
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