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WM8945ECS/R 数据表(PDF) 32 Page - Wolfson Microelectronics plc |
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WM8945ECS/R 数据表(HTML) 32 Page - Wolfson Microelectronics plc |
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32 / 169 page ![]() WM8945 Production Data w PD, May 2011, Rev 4.1 32 DSP CORE DSP Core is at the centre of the ADC / DAC / Digital Audio Interface (I2S) blocks. It provides signal routing, and also implements a number of configurable signal processing functions. The signal processing functions are arranged in three blocks, as follows: Signal Enhancement 1 (SE1) – Low-pass / High-pass filter, 5 notch filters, generic ‘Direct- Form 1’ filter. Signal Enhancement 2 (SE2) – ReTune™ processing, 5-band equalizer. Signal Enhancement 3 (SE3) – Dynamic range control The DSP Configuration modes and each of the Signal Enhancement blocks is described in the following sections. DSP CONFIGURATION MODES The DSP Configuration Mode is determined using the SE_CONFIG register field; this configures the signal paths between the Signal Enhancement blocks and the ADC / DAC / I2S interfaces. The supported DSP modes are illustrated in Figure 13. SE1 (LPF/HPF, 5-notch, DF1) SE2 (HPF, Re-Tune, 5-band EQ) SE3 (Dynamic Range Control) DAC L DIGITAL AUDIO INTERFACE ADC L SE1 (LPF/HPF, 5-notch, DF1) SE2 (HPF, Re-Tune, 5-band EQ) SE3 (Dynamic Range Control) DIGITAL AUDIO INTERFACE ADC L DAC L DSP Record Mode DSP Playback Mode Figure 13 DSP Configuration Modes |
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