WM8945ECSSLASHR datasheet(27/169 Pages) WOLFSON

27 / 169 page

Production Data

WM8945

PD, May 2011, Rev 4.1

DIGITAL MICROPHONE INTERFACE

The WM8945 supports a digital microphone interface, using the IN1L input pin for data and a GPIO

pin for the data clock. The analogue signal path from the IN1L pin must be disabled when using the

digital microphone interface; this is achieved by disabling the input PGA, (i.e. INPPGAL_ENA= 0).

The Digital Microphone Input, DMICDAT, is provided on the IN1L/DMICDAT pin. The associated

clock, DMICCLK, is provided on a GPIO pin.

The Digital Microphone Input is selected as input by setting the DMIC_ENA bit. When the Digital

Microphone Input is selected, the ADC input is deselected.

The digital microphone interface configuration is illustrated in Figure 11.

Note that the digital microphone may be powered from MICBIAS or from LDOVOUT; care must be

taken to ensure that the respective digital logic levels of the microphone are compatible with the

digital input thresholds of the WM8945. The digital input thresholds are referenced to DBVDD, as

defined in “Electrical Characteristics”.

Figure 11 Digital Microphone Interface

When any GPIO pin is configured as DMICCLK output, the WM8945 outputs a clock which supports

Digital Mic operation at the ADC sampling rate. The ADC and Record Path filters must be enabled

and the ADC sampling rate must be set in order to ensure correct operation of all DSP functions

associated with the digital microphone. Volume control for the Digital Microphone Interface signals is

provided using the ADC Volume Control.

See “Analogue-to-Digital Converter (ADC)” for details of the ADC Enable and volume control

functions. See “General Purpose Input / Output” for details of configuring the DMICCLK output. See

“Clocking and Sample Rates” for the details of the sample rate control.

When the DMIC_ENA bit is set, then the IN1L pin is used as the digital microphone input DMICDAT.

The interface requires that the digital microphone transmits a data bit each time that DMICCLK is

high. The WM8945 samples the data in the middle of the ‘high’ DMICCLK clock phase.

DMICCLK pin

DMICDAT pin

MIC output

hi-Z

Figure 12 Digital Microphone Interface Timing

WM8945ECS/R 数据表(PDF) 27 Page - Wolfson Microelectronics plc