ADE7759ARSRL datasheet(14/32 Pages) AD

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ADE7759

–14–

The ZX signal will go logic high on a positive going zero crossing

and logic low on a negative going zero crossing on Channel 2.

The zero crossing signal ZX is generated from the output of LPF1.

LPF1 has a single pole at 156 Hz (CLKIN = 3.579545 MHz).

As a result there will be a phase lag between the analog input

signal V2 and the output of LPF1. The phase response of this

filter is shown in the Channel 2 Sampling section of this data

sheet. The phase lag response of LPF1 results in a time delay of

approximately 0.97 ms (@ 60 Hz) between the zero crossing on

the analog inputs of Channel 2 and the rising or falling edge of ZX.

The zero crossing detection also has an associated time-out register,

ZXTOUT. This unsigned, 12-bit register is decremented 1 LSB

every 128/CLKIN seconds. The register is reset to its user pro-

grammed full-scale value every time a zero crossing on Channel 2

is detected. The default power on value in this register is FFFh.

If the register decrements to zero before a zero crossing is detected

and the DISSAG bit in the Mode register is logic zero, the

SAG

pin will go active low. The absence of a zero crossing is also

indicated on the

IRQ output if the SAG enable bit in the Inter-

rupt Enable register is set to Logic 1. Irrespective of the enable

bit setting, the SAG flag in the Interrupt Status register is always

set when the ZXTOUT register is decremented to zero—see Inter-

rupts section. The zero cross timeout register can be written/read

by the user and has an address of 0Eh—see Serial Interface section.

The resolution of the register is 128/CLKIN seconds per LSB.

Thus the maximum delay for an interrupt is 0.15 second

(128/CLKIN

× 212 ).

LINE VOLTAGE SAG DETECTION

In addition to the detection of the loss of the line voltage signal

(zero crossing), the ADE7759 can also be programmed to detect

when the absolute value of the line voltage drops below a certain

peak value, for a number of half cycles. This condition is illus-

trated in Figure 15.

FULL SCALE

SAGLVL [7:0]

SAG

SAG RESET HIGH

WHEN CHANNEL 2

EXCEEDS SAGLVL [7:0]

CHANNEL 2

SAGCYC [7:0] = 06H

6 HALF CYCLES

Figure 15. Sag Detection

Figure 15 shows the line voltage fall below a threshold that is set

in the Sag Level register (SAGLVL[7:0]) for nine half cycles.

Since the Sag Cycle register (SAGCYC[7:0]) contains 06h, the

SAG pin will go active low at the end of the sixth half cycle for

which the line voltage falls below the threshold, if the DISSAG

bit in the Mode register is logic zero. As is the case when zero

crossings are no longer detected, the sag event is also recorded

by setting the SAG flag in the Interrupt Status register. If the

SAG enable bit is set to Logic 1, the

IRQ logic output will go

active low—see Interrupts section.

The

SAG pin will go logic high again when the absolute value of

the signal on Channel 2 exceeds the sag level set in the Sag

Level register. This is shown in Figure 15 when the

SAG pin

goes high during the tenth half cycle from the time when the

signal on Channel 2 first dropped below the threshold level.

Sag Level Set

The contents of the Sag Level register (1 byte) are compared to

the absolute value of the most significant byte output from LPF1,

after it is shifted left by one bit. For example, the nominal maximum

code from LPF1 with a full-scale signal on Channel 2 is 257F6h

or (0010, 0101, 0111, 1111, 0110b)—see Channel 2 Sampling

section. Shifting one bit left will give 0100, 1010, 1111, 1110,

1100b or 4AFECh. Therefore writing 4Ah to the Sag Level

will put the sag detection level at zero. The Sag Level register is

compared to the most significant byte of a waveform sample

after the shift left, and detection is made when the contents of

the Sag Level register are greater.

POWER SUPPLY MONITOR

The ADE7759 also contains an on-chip power supply monitor. The

Analog Supply (AVDD) is continuously monitored by the ADE7759.

If the supply is less than 4 V

± 5%, the ADE7759 will go into an

inactive state, i.e., no energy will be accumulated when the supply

voltage is below 4 V. This is useful to ensure correct device operation

at power-up and during power-down. The power supply monitor

has built-in hysteresis and filtering. This gives a high degree of

immunity to false triggering due to noisy supplies.

AVDD

ADE7759

POWER-ON

RESET

SAG

INACTIVE

ACTIVE

INACTIVE

TIME

Figure 16. On-Chip Power Supply Monitor

As seen in Figure 16, the trigger level is nominally set at 4 V.

The tolerance on this trigger level is about

±5%. The SAG pin

can also be used as a power supply monitor input to the MCU.

The

SAG pin will go logic low when the ADE7759 is reset. The

power supply and decoupling for the part should be such that

the ripple at AVDD does not exceed 5 V

± 5% as specified for

normal operation.

Bit 6 of the Interrupt Status register (STATUS[7:0]) will be set to

Logic High upon power-up or every time the analog supply (AVDD)

dips below the power supply monitor threshold (4 V

± 5%) and

recovers. However, no interrupt can be generated because the corre-

sponding bit (Bit 6) in the Interrupt Enable register (IRQEN[7:0])

is not active—see Interrupts section.

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