ADE7759ARSRL datasheet(16/32 Pages) AD

16 / 32 page

REV. 0

ADE7759

–16–

TEMPERATURE MEASUREMENT

ADE7759 also includes an on-chip temperature sensor. A tem-

perature measurement can be made by setting Bit 5 in the Mode

ADE7759 will initiate a temperature measurement on the next

zero crossing. When the zero crossing on Channel 2 is detected,

the voltage output from the temperature sensing circuit is con-

nected to ADC1 (Channel 1) for digitizing. The resultant code is

processed and placed in the Temperature register (TEMP[7:0])

approximately 26

µs later (24 CLKIN cycles). If enabled in the

Interrupt Enable register (Bit 5), the

IRQ output will go active

low when the temperature conversion is finished. Please note that

temperature conversion will introduce a small amount of noise

in the energy calculation. If temperature conversion is performed

frequently (i.e., multiple times per second), a noticeable error

will accumulate in the resulting energy calculation over time.

The contents of the Temperature register are signed (two’s

complement) with a resolution of approximately 1 LSB/

°C. The

temperature register will produce a code of 00h when the ambient

temperature is approximately 70

°C. The temperature mea-

surement is uncalibrated in the ADE7759 and has an offset

tolerance that could be as high as

±20°C.

ANALOG-TO-DIGITAL CONVERSION

The analog-to-digital conversion in the ADE7759 is carried out

using two second order sigma-delta ADCs. The block diagram

in Figure 19 shows a first order (for simplicity) sigma-delta ADC.

The converter is made up of two parts, first the sigma-delta

modulator and second the digital low-pass filter.

A sigma-delta modulator converts the input signal into a con-

tinuous serial stream of 1s and 0s at a rate determined by the

sampling clock. In the ADE7759, the sampling clock is equal to

CLKIN/4. The 1-bit DAC in the feedback loop is driven by the

serial data stream. The DAC output is subtracted from the

input signal. If the loop gain is high enough, the average value of

the DAC output (and therefore the bitstream) will approach that

of the input signal level. For any given input value in a single sam-

pling interval, the data from the 1-bit ADC is virtually meaningless.

Only when a large number of samples are averaged will a meaningful

result be obtained. This averaging is carried out in the second

part of the ADC, the digital low-pass filter. By averaging a large

number of bits from the modulator, the low-pass filter can produce

20-bit data words that are proportional to the input signal level.

DIGITAL

LOW-PASS

FILTER

ANALOG

LOW-PASS FILTER

–

∫

VREF

1-BIT DAC

MCLK/4

LATCHED

COMPARATOR

.....10100101.....

–

Figure 19. First Order Sigma-Delta (

Σ-∆) ADC

The sigma-delta converter uses two techniques to achieve high

resolution from what is essentially a one-bit conversion technique.

The first is oversampling. By oversampling we mean that the

signal is sampled at a rate (frequency) that is many times higher

than the bandwidth of interest. For example, the sampling rate

in the ADE7759 is CLKIN/4 (894 kHz) and the band of interest

is 40 Hz to 2 kHz. Oversampling has the effect of spreading the

quantization noise (noise due to sampling) over a wider bandwidth.

With the noise spread more thinly over a wider bandwidth, the

quantization noise in the band of interest is lowered—see Figure

20. However, oversampling alone is not an efficient enough

method to improve the signal to noise ratio (SNR) in the band

of interest. For example, an oversampling ratio of 4 is required

just to increase the SNR by only 6 dB (one bit). To keep the

oversampling ratio at a reasonable level, it is possible to shape the

quantization noise so that the majority of the noise lies at the higher

frequencies. This is what happens in the sigma-delta modulator:

the noise is shaped by the integrator, which has a high-pass type

response for the quantization noise. The result is that most of

the noise is at the higher frequencies, where it can be removed

by the digital low-pass filter. This noise shaping is also shown in

Figure 20.

447

894

NOISE

SIGNAL

DIGITAL

FILTER

ANTIALIAS

FILTER (RC)

SHAPED

NOISE

SAMPLING

FREQUENCY

447

894

NOISE

SIGNAL

HIGH RESOLUTION

OUTPUT FROM DIGITAL

LPF

FREQUENCY – kHz

Figure 20. Noise Reduction Due to Oversampling

and Noise Shaping in the Analog Modulator

Antialias Filter

Figure 20 also shows an analog low-pass filter (RC) on the input

to the modulator. This filter is present to prevent aliasing.

Aliasing is an artifact of all sampled systems. Basically it means

that frequency components in the input signal to the ADC that

are higher than half the sampling rate of the ADC will appear in

the sampled signal at a frequency below half the sampling rate.

Figure 21 illustrates the effect. Frequency components (arrows

shown in black) above half the sampling frequency (also known as

the Nyquist frequency, i.e., 447 kHz) get imaged or folded back

down below 447 kHz (arrows shown in grey). This will happen

with all ADCs regardless of the architecture. In the example

shown, it can be seen that only frequencies near the sampling

frequency (894 kHz) will move into the band of interest for

metering, i.e., 40 Hz–2 kHz. This allows us to use a very simple

LPF (low-pass filter) to attenuate these high frequencies (near

900 kHz) and to prevent distortion in the band of interest. For a

conventional current sensor, a simple RC filter (single pole) with

a corner frequency of 10 kHz will produce an attenuation of

approximately 40 dBs at 894 kHz—see Figure 20. The 20 dB per

decade attenuation is usually sufficient to eliminate the effects of

aliasing for conventional current sensor.

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