ADE7759ARSRL datasheet(28/32 Pages) AD

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ADE7759

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Table IV. Register List

Address

Name

R/W

# of Bits

Default

Description

01h

WAVEFORM

24/40

The Waveform register is a read-only register. This register contains

the sampled waveform data from Channel 1, Channel 2, or the Active

Power signal. The data source and the length of the Waveform regis-

ters are selected by data bits 14 and 13 in the Mode Register—see

Channel 1 and 2 Sampling section.

02h

AENERGY

The Active Energy Register. Active Power is accumulated (Integrated)

over time in this 40-bit, read-only register. The energy register can hold

a minimum of 11.53 seconds of Active Energy information with full-

scale analog inputs before it overflows—see Energy Calculation section.

03h

RSTENERGY

Same as the Active Energy Register except that the register is reset to 0

following a read operation.

04h

STATUS

40h

Interrupt Status Register. This is an 8-bit read-only register. The status

rupts—see Interrupts section.

05h

RSTSTATUS

Same as the Interrupt Status Register except that the register contents

are reset to 0 (all flags cleared) after a read operation.

06h

MODE

R/W

000Ch

The Mode Register. This is a 16-bit register through which most of the

ADE7759 functionality is accessed. Signal sample rates, filter enabling

and calibration modes are selected by writing to this register. The

contents may be read at any time—see Mode Register section.

07h

CFDEN

R/W

3Fh

CF Frequency Divider Denominator Register. The output frequency

on the CF pin is adjusted by writing to this 12-bit read/write register—

see Energy-to-Frequency Conversion section.

08h

CH1OS

R/W

80h

Channel 1 Offset Adjust. The MSB is used to enable the digital integra-

tor. Bit 6 is not used. Writing to Bit 0 to 5 allows offsets on Channel 1

to be removed—see Analog Inputs section and CH1OS Register section.

09h

CH2OS

R/W

Channel 2 Offset Adjust. Writing to this 6-bit register allows any offsets

on Channel 2 to be removed—see Analog Inputs section.

0Ah

GAIN

R/W

PGA Gain Adjust. This 8-bit register is used to adjust the gain selec-

tion for the PGA in Channel 1 and 2—see Analog Inputs section.

0Bh

APGAIN

R/W

Active Power Gain Adjust. This is a 12-bit register. The Active Power

calculation can be calibrated by writing to this register. The calibration

range is

±50% of the nominal full-scale active power. The resolution of the

gain adjust is 0.0244%/LSB—see Channel 1 ADC Gain Adjust section.

0Ch

PHCAL

R/W

Phase Calibration Register. The phase relationship between Channel 1

and Channel 2 can be adjusted by writing to this 8-bit register. The

valid content of this two’s complement register is between 9Eh and

5Ch, which is a phase difference of –2.365

° to +2.221° at 60 Hz in

0.0241

° steps—see Phase Compensation section.

0Dh

APOS

R/W

Active Power Offset Correction. This 16-bit register allows small off-

sets in the Active Power calculation to be removed—see Active Power

Calculation section.

CHECKSUM REGISTER

The ADE7759 has a Checksum register (CHKSUM[5:0]) to

ensure the data bits received in the last serial read operation are

not corrupted. The 6-bit Checksum register is reset before the

first bit (MSB of the register to be read) is put on the DOUT

pin. During a serial read operation, when each data bit becomes

available on the rising edge of SCLK, the bit will be added to

the Checksum register. In the end of the serial read operation,

the content of the Checksum register will be the sum of all the ones

contained in the register previously read. Using the Checksum

the last read operation.

Note that a read to the CHKSUM register will also generate a

checksum of the CHKSUM register itself.

CONTENT OF REGISTER (n-bytes)

CHECKSUM REGISTER

ADDR: 1Eh

DOUT

Figure 47. Checksum Register for Serial Interface Read

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