REV. 0

ADE7759

–31–

0

000

000

0

000

01

10

0

15 14 13 12 11 10

98765

4

3210

ADDR: 06H

DISHPF

(DISABLE HPF1 IN CHANNEL 1)

DISLPF2

(DISABLE LPF2 AFTER MULTIPLIER)

DISCF

(DISABLE FREQUENCY OUTPUT CF)

DISSAG

(DISABLE

SAG OUTPUT)

ASUSPEND

(SUSPEND CH1 AND CH2 ADC’s)

STEMP

(START TEMPERATURE SENSING)

SWRST

(SOFTWARE CHIP RESET)

CYCMODE

(LINE CYCLE ENERGY ACCUMULATION MODE)

TEST1

(TEST MODE SELECTION SHOULD BE SET TO 0)

WAVSEL

(WAVEFORM SELECTION FOR SAMPLE MODE)

00 = LPF2

01 = CH1 + CH2 (40-BIT WAVEFORM SAMPLES)

10 = CH1

11 = CH2

DTRT

(WAVEFORM SAMPLES OUTPUT DATA RATE)

00 = 27.9kSPS (CLKIN/128)

01 = 14.4kSPS (CLKIN/256)

10 = 7.2kSPS (CLKIN/512)

11 = 3.6kSPS (CLKIN/1024)

SWAP

(SWAP CH1 AND CH2 ADCs)

DISCH2

(SHORT THE ANALOG INPUTS ON CHANNEL 2)

DISCH1

(SHORT THE ANALOG INPUTS ON CHANNEL 1)

NOTE: REGISTER CONTENTS SHOW POWER-ON DEFAULTS

Figure 48. Mode Register

Interrupt Status Register (04H)/Reset Interrupt Status Register (05H)

The Status register is used by the MCU to determine the source of an interrupt request (

IRQ). When an interrupt event occurs in the

ADE7759, the corresponding flag in the Interrupt Status register is set logic high. If the enable bit for this flag is Logic 1 in the Inter-

rupt Enable register, the

IRQ logic output goes active low. When the MCU services the interrupt, it must first carry out a read from

the Interrupt Status register to determine the source of the interrupt.

Table VII. Interrupt Status Register, Reset Interrupt Status Register, and Interrupt Enable Register

Bit

Interrupt

Location

Flag

Description

0

AEHF

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Active Energy register.

1

SAG

Indicates that an interrupt was caused by a SAG on the line voltage or no zero crossings were detected.

2

CYCEND

Indicates the end of energy accumulation over an integer number of half line cycles as defined by

the content of the LINECYC register—see Line Cycle Energy Accumulation Mode section.

3

WSMP

Indicates that new data is present in the Waveform register.

4

ZX

This status bit reflects the status of the ZX logic ouput—see Zero Crossing Detection section.

5

TEMP

Indicates that a temperature conversion result is available in the Temperature register.

6

RESET

Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has

no function in the Interrupt Enable register, i.e., this status bit is set at the end of a reset, but it

cannot be enabled to cause an interrupt.

7

AEOF

Indicates that the Active Energy register has overflowed.

010

00

00

0

765

4

3210

ADDR: 04H/RESET: 05H

AEHF

(ACTIVE ENERGY REGISTER HALF FULL)

SAG

(LINE VOLTAGE SAG DETECT)

CYCEND

(LINE CYCLE ENERGY ACCUMULATION END)

WSMP

(WAVEFORM SAMPLING)

AEOF

(ACTIVE ENERGY REGISTER OVERFLOW)

TEMP

(TEMPERATURE REGISTER READY)

ZX

(ZERO CROSSING DETECTED)

RESET

(END OF A HARDWARE OR SOFTWARE RESET)

NOTE: REGISTER CONTENTS SHOW POWER ON DEFAULTS

Figure 49. Interrupt Status Register