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ADE7759ARSRL 数据表(PDF) 32 Page - Analog Devices

部件名 ADE7759ARSRL
功能描述  Active Energy Metering IC with di/dt Sensor Interface
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7759ARSRL 数据表(HTML) 32 Page - Analog Devices

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REV. 0
–32–
ADE7759
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Shrink Small Outline Package
(RS-20)
0.037 (0.94)
0.022 (0.559)
0.009 (0.229)
0.005 (0.127)
8
0
0.295 (7.50)
0.271 (6.90)
0.311 (7.9)
0.301 (7.64)
0.212 (5.38)
0.205 (5.21)
20
11
10
1
PIN 1
0.0256
(0.65)
BSC
0.008 (0.203)
0.002 (0.050)
0.07 (1.78)
0.066 (1.67)
0.078 (1.98)
0.068 (1.73)
SEATING
PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
000
00
00
0
765
4
3210
ADDR: 10H
AEHF
(ACTIVE ENERGY REGISTER HALF FULL)
SAG
(LINE VOLTAGE SAG DETECT)
CYCEND
(END OF LINE CYCLE ENERGY ACCUMULATION)
WSMP
(WAVEFORM SAMPLING)
AEOF
(ACTIVE ENERGY REGISTER OVERFLOW)
NOT USED
TEMP
(TEMPERATURE REGISTER READY)
ZX
(ZERO CROSSING DETECTED)
NOTE: REGISTER CONTENTS SHOW POWER ON DEFAULTS
Figure 50. Interrupt Enable Register
CH1OS Register (08H)
The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch on/off the digital integrator in
Channel 1, and Bits 0 to 5 indicate the amount of the offset correction in Channel 1. Table VIII summarizes the function of this register.
Table VIII. CH1OS Register
Bit Location
Bit Mnemonic
Description
0 to 5
OFFSET
The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1
ADC. The 6-bit offset correction is sign and magnitude coded. Bits 0 to 4 indicate the magnitude
of the offset correction. Bit 5 shows the sign of the offset correction. A 0 in Bit 5 means the
offset correction is positive and a 1 indicates the offset correction is negative.
6
Not Used
This bit is unused.
7
INTEGRATOR
This bit is used to activate the digital integrator on Channel 1. The digital integrator is switched
on by setting this bit. This bit is set to be 1 on default.
100
00
00
0
765
4
3210
ADDR: 08H
CH1OS REGISTER*
SIGN AND MAGNITUDE CODED
OFFSET CORRECTION BITS
DIGITAL INTEGRATOR SELECTION
1 = ENABLE
0 = DISABLE
NOT USED
*REGISTER CONTENTS SHOW POWER-ON DEFAULT
Figure 51. CH1OS Register



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