ADE7759ARSRL datasheet(27/32 Pages) AD

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REV. 0

ADE7759

–27–

DIN

SCLK

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

DB7

DB0

DB7

DB0

Figure 44. Serial Interface Write Timing Diagram

SCLK

DIN

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 45. 12-Bit Serial Write Operation

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

SCLK

t10

t13

DB0

DB7

DB0

DB7

DIN

DOUT

t11

t12

Figure 46. Serial Interface Read Timing Diagram

As explained earlier, the data write is initiated by a write to the

communications register followed by the data. During a data

write operation to the ADE7759, data is transferred to all on-

chip registers one byte at a time. After a byte is transferred into

the serial port, there is a finite time before it is transferred to

one of the ADE7759 on-chip registers. Although another byte

transfer to the serial port can start while the previous byte is

being transferred to an on-chip register, this second byte transfer

should not finish until at least 4

µs after the end of the previous

byte transfer. This functionality is expressed in the timing speci-

fication t6—see Figure 44. If a write operation is aborted during

a byte transfer (

CS brought high), then that byte will not be

written to the destination register.

Destination registers may be up to 3 bytes wide—see Register

Description section. Hence the first byte shifted into the serial

port at DIN is transferred to the MSB (Most Significant Byte)

of the destination register. If the addressed register is 12 bits

wide, for example, a two-byte data transfer must take place. The

data is always assumed to be right justified: therefore in this

case, the four MSBs of the first byte would be ignored and the

four LSBs of the first byte written to the ADE7759 would be the

four MSBs of the 12-bit word. Figure 45 illustrates this example.

Serial Read Operation

During a data read operation from the ADE7759, data is shifted

out at the DOUT logic output on the rising edge of SCLK. As

was the case with the data write operation, a data read must be

preceded with a write to the Communications register.

With the ADE7759 in communications mode (i.e.,

CS logic low),

an 8-bit write to the Communications register first takes place.

The MSB of this byte transfer is a 0, indicating that the next

data transfer operation is a read. The LSBs of this byte contain

the address of the register that is to be read. The ADE7759 starts

shifting out of the register data on the next rising edge of SCLK—

see Figure 46. At this point the DOUT logic output leaves its

high impedance state and starts driving the data bus. All remain-

ing bits of register data are shifted out on subsequent SCLK

rising edges. The serial interface also enters communications

mode again as soon as the read has been completed. At this

point the DOUT logic output enters a high impedance state on

the falling edge of the last SCLK pulse. The read operation may

be aborted by bringing the

CS logic input high before the data

transfer is complete. The DOUT output enters a high imped-

ance state on the rising edge of

CS.

When an ADE7759 register is addressed for a read operation,

the entire contents of that register are transferred to the serial

port. This allows the ADE7759 to modify its on-chip registers

without the risk of corrupting data during a multi byte transfer.

Note when a read operation follows a write operation, the read

command (i.e., write to Communications register) should not

happen for at least 4

µs after the end of the write operation. If the

read command is sent within 4

µs of the write operation, the last

byte of the write operation may be lost. This timing constraint is

given as timing specification t9.

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