PCF8523TSLASH1 datasheet(37/75 Pages) NXP

37 / 75 page

PCF8523

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Product data sheet

Rev. 4 — 5 July 2012

37 of 74

NXP Semiconductors

PCF8523

Real-Time Clock (RTC) and calendar

At the end of every countdown, the timer sets the countdown timer flag CTAF (register

Control_2). CTAF may only be cleared by using the interface. Instructions, how to clear a

flag, is given in Section 8.7.5.

When reading the timer, the current countdown value is returned and not the initial

value n. Since it is not possible to freeze the countdown timer counter during read back, it

is recommended to read the register twice and check for consistent results.

If a new value of n is written before the end of the actual timer-period, this value takes

immediate effect. It is not recommended to change n without first disabling the counter by

setting TAC[1:0] = 00 (register Tmr_CLKOUT_ctrl). The update of n is asynchronous to

the timer clock. Therefore changing it on the fly could result in a corrupted value loaded

into the countdown counter. This can result in an undetermined countdown period for the

first period. The countdown value n will be correctly stored and correctly loaded on

subsequent timer-periods.

Loading the counter with 0 effectively stops the timer.

When starting the countdown timer for the first time, only the first period does not have a

fixed duration. The amount of inaccuracy for the first timer-period depends on the chosen

source clock, see Table 41.

The generation of interrupts from the countdown timer is controlled via the CTAIE bit

(register Control_2).

In this example, it is assumed that the countdown timer flag (CTAF) is cleared before the next

countdown period expires and that the interrupt output is set to pulse mode.

Fig 20. General countdown timer behavior

Table 41.

First period delay for timer counter value n

Timer source clock

Minimum timer-period

Maximum timer-period

4.096 kHz

n + 1

64 Hz

n + 1

1 Hz

 1) + 1⁄

64 Hz

n + 1⁄64 Hz

1⁄60 Hz

 1) + 1⁄

64 Hz

n + 1⁄64 Hz

1⁄3600 Hz

 1) + 1⁄

64 Hz

n + 1⁄64 Hz

013aaa328

countdown value, n

timer source clock

countdown counter

WD/CD [1:0]

CTAF

INT1

duration of first timer period after

enable may range from n

−1 to n+1

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