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PCF8523T/1 数据表(PDF) 46 Page - NXP Semiconductors |
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PCF8523T/1 数据表(HTML) 46 Page - NXP Semiconductors |
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46 / 75 page  PCF8523 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 — 5 July 2012 46 of 74 NXP Semiconductors PCF8523 Real-Time Clock (RTC) and calendar The PCF8523 can act as a slave transmitter and a slave receiver. 8.11.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge cycle after the reception of each byte • Also a master receiver must generate an acknowledge cycle after the reception of each byte that has been clocked out of the slave transmitter • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the related acknowledge clock pulse (set-up and hold times must be considered) • A master receiver must signal an end of data to the transmitter by not generating an acknowledge cycle on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition Acknowledgement on the I2C-bus is shown in Figure 31. 8.11.5 I2C-bus protocol One I2C-bus slave address (1101000) is reserved for the PCF8523. The entire I2C-bus slave address byte is shown in Table 46. Fig 30. System configuration mba605 MASTER TRANSMITTER RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER RECEIVER SDA SCL Fig 31. Acknowledgement on the I2C-bus mbc602 S START condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver SCL from master |
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