LMP91051

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SNAS581A – MARCH 2012 – REVISED NOVEMBER 2012

Electrical Characteristics

(1) (continued)

Min

Typ

Max

Symbol

Parameter

Conditions

Units

(2)

(3)

(2)

Phase Delay variation with

250mV input step signal, Gain = 8, Vout

TCPhDly

84

ns

Temperature

measured at Vdd/2

SSBW

Small Signal Bandwidth

Gain = 32 V/V

360

kHz

Cin

Input Capacitance

5

pF

CLOAD,

OUT Pin Load Capacitance

Series RC

1

µF

OUT

RLOAD,

OUT Pin Load Resistance

Series RC

1

k

Ω

OUT

Combined Amplifier Chain Specification

Combination of both current and voltage noise,

en

Input-Referred Noise Density

with a 86k

Ω source impedance at 5Hz, Gain =

30

nV

√Hz

7986

Combination of both current and voltage noise,

0.12

Input-Referred Integrated Noise with a 86k

Ω source impedance 0.1Hz to 10Hz,

0.1

µVrms

(4)

Gain = 7986

PGA1 GAIN = 42, PGA2 GAIN = 4

167

PGA1 GAIN = 42, PGA2 GAIN = 8

335

PGA1 GAIN = 42, PGA2 GAIN = 16

669

PGA1 GAIN = 42, PGA2 GAIN = 32

1335

G

Gain

V/V

PGA1 GAIN = 250, PGA2 GAIN = 4

1002

PGA1 GAIN = 250, PGA2 GAIN = 8

2004

PGA1 GAIN = 250, PGA2 GAIN = 16

4003

PGA1 GAIN = 250, PGA2 GAIN = 32

7986

GE

Gain Error

Any gain

5

%

Gain = 167 V/V, 335 V/V, 669 V/V, 1335 V/V

6

ppm/°C

TCCGE

Gain = 1002 V/V, 2004 V/V, 4003 V/V, 7986V/V

20

ppm/°C

PSRR

Power Supply Rejection Ratio

DC, 3.0V to 3.6V supply, gain = 1002V/V

90

110

dB

1mV input step signal, Gain = 1002, Vout

PhDly

Phase Delay

measured at Vdd/2

9

µs

Phase Delay variation with

1mV input step signal, Gain=1002, Vout

TCPhDly

measured at Vdd/2

300

ns

Gain = 167 V/V

70

Gain = 335 V/V

100

Gain = 669 V/V

160

Gain = 1335 V/V

290

Output Offset Voltage

TCVOS

μV/°C

Gain = 1002 V/V

230

Gain = 2004 V/V

420

Gain = 4003 V/V

800

Gain = 7986V/V

1550

Common Mode Generator

VDD = 3.3V

1.15

VCM

Common Mode Voltage

V

VDD = 5V

2.59

VCM accuracy

2

%

CLOAD

CMOut Load Capacitance

10

nF

(4)

Guaranteed by design and characterization. Not tested on shipped production material.

(5)

TCCGE and TCVOS are calculated by taking the largest slope between -40°C and 25°C linear interpolation and 25°C and 85°C linear

interpolation.

(6)

TCPhDly is largest change in phase delay between -40°C and 25°C measurements and 25°C and 85°C measurements.

Copyright © 2012, Texas Instruments Incorporated

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