c7

c6

c5

c4

c3

c2

c1

c0

d7

d6

d5

d4

d3

d2

d1

d0

CSB

SCK

COMMAND FIELD

DATA FIELD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

LSB

MSB

Reserved to 0

Address (4 bits)

Write Data (8-bits)

Wb=0

LMP91051

SNAS581A – MARCH 2012 – REVISED NOVEMBER 2012

www.ti.com

CSB

Chip Select is a active-low signal. CSB needs to be asserted throughout a transaction. That is, CSB should not

pulse between the Instruction Byte and the Data Byte of a single transaction.

Note that CSB de-assertion always terminates an on-going transaction, if it is not already complete. Likewise,

CSB assertion will always bring the device into a state, ready for next transaction, regardless of the termination

status of a previous transaction.

CSB may be permanently tied low for a 2-wire SPI communication protocol.

SCLK

SCLK can idle High or Low for a write transaction. However, for a READ transaction, SCLK should idle high.

SCLK features a Schmitt-triggered input and although it has hysterisis, it is recommened to keep SCLK as clean

as possible to prevent glitches from inadvertently spoiling the SPI frame.

Communication Protocol

Communication on the SPI normally involves Write and Read transactions. Write transaction consists of single

Write Command Byte, followed by single Data byte. The following figure shows the SPI Interface Protocol for

write transaction.

Figure 11. SPI Interface Protocol

For Read transactions, user first needs to write into a SDIO mode enable register for enabling the SPI read

mode. Once the device is enabled for Reading, the data is driven out on the SDIO pin during the Data field of the

Read Transaction. SDIO pin is designed as a bidirectional pin for this purpose. Figure 6 shows the Read

transaction. The sequence of commands that need to be issued by the SPI Master to enable SPI read mode is

illustrated in Figure 13.

16

Copyright © 2012, Texas Instruments Incorporated

Product Folder Links: LMP91051