10 PF

160 k:

160 k:

6.8 nF

CMOUT

A0

A1

LMP91051

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SNAS581A – MARCH 2012 – REVISED NOVEMBER 2012

Table 2. Gain Modes

Bit Symbol

Gain

0: 250 (default)

GAIN1

1: 42

00: 4 (default)

01: 8

GAIN2 [1:0]

10: 16

11: 32

EXTERNAL FILTER

The LMP91051 offers two different measurement modes selectable through EXT_FILT bit. EXT_FILT bit is

present in the Device configuration register and is programmable through SPI.

Table 3. Measurement Modes

Bit Symbol

Measurement Mode

EXT_FILT

0: The signal from the thermopile is being processed by the internal PGAs, without

additional external decoupling or filtering (default).

1: The signal from the thermopile is being processed by the first internal PGA and fed to the A0

pin. An external low pass, high pass or band pass filter can be connected through pins A0, A1.

An external filter can be applied when EXT_FILT = 1. A typical band pass filter is shown in the picture below.

Resistor and capacitor can be connected to the CMOUT pin of the LMP91051 as shown. Discrete component

values have been added for reference.

Figure 10. Typical Bandpass Filter

OFFSET ADJUST

Procedure of the offset adjust is to first measure the “dark signal”, program the DAC to adjust, and then measure

in a second cycle the residual of the dark signal for further signal manipulation within the µC. The signal source

is expected to have an offset component (dark signal) larger than the actual signal. During the “dark phase”, the

time when no light is detected by the sensor, the µC can program LMP91051 internal DAC to compensate for a

measured offset. A low output offset voltage temperature drift (TCVOS) ensures system accuracy over

temperature.

COMMON MODE GENERATION

As the sensor's offset is bipolar, there is a need to supply a VCM to the sensor. This can be programmed as

1.15V or 2.59V (approximately mid rail of 3.3V or 5V supply). It is not recommended to use 2.59V VCM with 3.3V

supply

SPI INTERFACE

An SPI interface is available in order to program the device parameters like PGA gain of two stages, enabling

external filter, enabling power for PGAs, offset adjust and common mode (VCM) voltage.

Interface Pins

The Serial Interface consists of SDIO (Serial Data Input / Output), SCLK (Serial Interface Clock) and CSB (Chip

Select Bar). The serial interface is write-only by default. Read operations are supported after enabling the SDIO

mode by programming the SDIO_MODE_EN register. This is discussed in detail later in the document.

Copyright © 2012, Texas Instruments Incorporated

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