ACT7006 datasheet(8/29 Pages) AEROFLEX

8 / 29 page

Aeroflex Circuit Technology

SCD7005 REV B 8/2/01

Plainview NY (516) 694-6700

SINGLE HYBRID

PROTOCOL SUBSYSTEM INTERFACE

KEY FEATURES

• Functional Superset of CT1800

• Downward compatible with existing designs base

of CT1800

• Incorporates Transceivers, Protocol and Interface

Hybrids into a single package

• Functions as a Remote Terminal or Bus Controller

GENERAL

The ACT7005/6 Series provides a complete

interface between the MIL-STD-1553 bus and any

micro-processor system. Functioning as a superset

of the CT1800 interface, the hybrid provides all data

buffers and control registers necessary to implement

RT and BC functions. Internal arbitration and data

transfer control circuitry eliminates subsystem

response requirements. All data written into or read

from this interface are double buffered on a message

basis. Only valid and complete receive messages

are transferred into the receive RAM.

The ACT7005/6 Series supports all 15 mode codes

and all types of data transfers allowed by

MIL-STD-1553B. All circuitry (excluding transceiver

drivers) are CMOS, which results in very low power

requirements.

Interfacing to the subsystem is simplified through

the use of tri-stated input/output buffers onto the

subsystem bus. Control signals basically consist of

four address lines, a device select input, read strobe,

write strobe, and several interrupts, the use of which

are optional. The Hybrid is accessed as a memory

mapped I/O port of a microprocessor system. Valid

transmission and reception of data are indicated to

the subsystem through the use of interrupts. This

frees up the system processor from actively

monitoring the port until a valid message is received.

OPERATION

The ACT7005/6 Series (Single Package Solution)

resides between a microprocessor interface and a

MIL-STD-1553 data bus. The addition of two

transformers and fault isolation resistors are the only

external components required to complete the

interface. Information on the bus is received or

transmitted through the transceiver (converted from

Manchester II to complimentary TTL signals and

visa versa) to the protocol section. The ACT7005/6

Series incorporates a single +5VDC only

transceiver.

The protocol section internally interfaces to the

transceivers. Control of the transceivers is provided

by the protocol section. This is determined by which

bus the command word was received on in the

remote terminal mode; or in the bus controller mode,

which bus was selected for transmission by the state

of a bit in the operation register. An autonomous

self-test can be performed either off-line or on-line

through the transceivers This self-test is controlled

by the operation register and will be discussed

thoroughly in the self-test section. The other test

function is that in addition to the protocol criteria that

is tested during every transmission; i.,e., proper sync

character, 16 data bits, Manchester II coded,

contiguous words, and odd parity, a bit per bit

comparison of the contents of the parallel data will

insure a higher degree of functionality of this section

of the hybrid.

Data received by the protocol section will be placed

in the receive FIFO buffer. Transmitted data will be

taken from the transmit FIFO buffer. Other than the

remote terminal address and parity, the discretes to

control the resetting of the terminal flag and

subsystem error bits, and a few discrete interrupts

and error signals, control over the protocol section

resides in the operation register of the subsystem

interface section.

The subsystem interface section has primary

control of the data that resides in the 2k of RAM. The

RAM is segregated into two 1k blocks of data, one

contains 30 blocks of transmit data messages and

the other one contains 30 blocks of receive data

messages. This is not absolute since the subsystem

has control of the A10 bit. Data entries to or from the

RAM are arbitrated by the control logic residing in

this function, and is buffered via FlFO’s on the input

from the protocol section and on the output to the

subsystem’s data bus. This guarantees that only

current and valid data blocks will reside in RAM. This

is true for remote terminal and bus controller

applications.

Seven dedicated registers are provided to ease the

interfacing with the subsystem. These will be

discussed in the Register Operation section of this

document. The register of primary concern to a

subsystem designer is the operation register. This

provides the means to accomplish data transfers to/

from the RAM, as well as control of remote terminal

or bus control modes of operation. All registers are

accessed via simple l/O commands, utilizing A0

through A3, Device Select, and Read or Write

strobes.

Receive Commands

When a valid receive command is received, it is first

loaded into the Command Word Register. The data

words associated with this command are received,

validated, and loaded one by one into the RCV FIFO

buffer. Once the entire message is received, and

only if the complete block of data is valid, will the

ACT7006 数据表(PDF) 8 Page - Aeroflex Circuit Technology

ACT7006 数据表(HTML) 8 Page - Aeroflex Circuit Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

数据表下载