ACT7006 datasheet(9/29 Pages) AEROFLEX

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SCD7005 REV B 8/2/01

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command word be transferred to the RCV Command

internal controller) into the corresponding internal

RAM location, which is memory mapped by the

subaddress contained in the RCV Command

interrupt pulse called INT #1 is sent the subsystem.

If this interrupt is used, the subsystem would read

the command word from the RCV Command

OUTPUT FIFO buffer, and read by the subsystem.

Each receive subaddress section of the internal

RAM will contain only the most recent, valid, and

complete block of data to that subaddress. This is

true for Remote Terminal and Bus Controller

operations.

Transmit Commands

If a valid transmit command is received, the

command word is first loaded into the Command

Word Register. The block of data corresponding to

the subaddress of the transmit command is then

transferred from the internal RAM to the XMIT FIFO

buffer. Upon completion of this transfer, INT #2 is

sent to the subsystem.

The transmit section of the internal RAM is

generally initialized at power up and periodically

updated as required.

Appropriate subsystem response to INT #2 for an

RT implementation would be to read the command

word from the Command Word Register. The data to

this subaddress could now be refreshed in

preparation for the next time it was requested to be

transmitted across the 1553 bus.

Mode Codes

All 15 mode codes are serviced by the protocol

section, and most do not require subsystem

intervention. Discrete interrupt signals are available

for each of the Synchronize (with and without data),

Vector Word, Reset, and Dynamic Bus Control

Acceptance mode codes. Mode command words are

loaded into the Command Word Register. Separate

registers are provided for the synchronize data word

and the vector data words.

Bus Control Operation

Upon initialization of power to the ACT7005/6

Series, all registers are reset. The operation register

is reset to FF80H; this setting defaults to the remote

terminal mode of operation with the Busy Bit set. To

enter into the Bus Control Mode of operation, bit 8 of

the operation register must be asserted low. While in

this mode, the upper byte (8 bits) of the operation

includes TEST/NORMAL operation, RT to RT

commands, BUS selection and RETRY initialization

of a faulty transaction.

A typical Bus Control transaction would operate as

follows: All areas of internal RAM that will be used

for transmission are initialized by the subsystem with

the desired data. To accomplish this, the subsystem

will first WRITE to the INPUT buffer the number of

words to be transferred. This information is now

transferred to the internal RAM under control of the

OPERATION register by specifying the subaddress

bits 0-4, setting the T/R bit (bit 5) and l/O bit (bit 6)

high. This will be executed by issuing an EXECUTE

operation l/O command. When the transfer has been

completed, the DONE interrupt will pulse low, and

valid data will now reside in this RAM location. Next,

the subsystem will write the command word to

COMMAND WORD #1 register. If it were an

RT-to-RT transfer, the transmitting RT command

word would be written into COMMAND WORD #2

the OPERATION register, which controls which bus

to transmit on and if retry will be an option. This

information will be enacted upon when the

subsystem issues a TRIGGER I/O command. The

return status word from the remote terminal or status

words for RT-to-RT transfers will reside in their

appropriate registers upon the issuance of INT #1. If

the RETRY option had been selected and a valid

transfer had not occurred, the RETRY interrupt

would have occurred instead of INT #1. Three retrys

are the maximum number allowed. The retrys can be

accomplished on the primary or secondary bus

determined by programming bits in the operation

A retry will be initiated if the retry bits are set in the

OPERATION register. The criteria for attempting a

retry is the lack of a returned status word or returned

mode data, or that 768µsec has transpired since the

start of the data transfer. A retry will not be executed

if bits are set in the return status word(s); this is up to

the subsystem to interpret the status word contents

and to reinitiate the transfer if desired.

Discrete Interrupts

Twelve discrete interrupt output signals are

available for the subsystem interface. Any or all of

these may be used depending on subsystem

requirements. Excluding the signal BUFF EF, all

interrupts are low going pulse signals. Interrupt and

status signals RESET, DBCREQ, and NBGT are

500ns wide nominally, and VECTOR is typically

1.5µs wide. All remaining interrupts are nominally

160ns.

The output buffer empty flag (BUFF EF), which is a

level, is also made available for subsystem use.

When low, it indicates the output buffer is empty. See

Table 6 for additional information.

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