ACT7006 datasheet(11/29 Pages) AEROFLEX

11 / 29 page

Aeroflex Circuit Technology

SCD7005 REV B 8/2/01

Plainview NY (516) 694-6700

parity, and contiguous word checking), but also the

inclusion of a bit by bit comparison of transmitted

data has been added. The added circuitry is used to

insure that the internal functional blocks, encoder,

decoder, and internal control circuitry are functioning

properly. The internal data path can be verified as

fault free by comparing the returned data word with

the supplied data. The most effective data pattern to

accomplish this is HEX AA55, since each bit is

toggled (8 bit internal highway) on a high/low byte

basis. Total time to complete the test is 89

microseconds. TEST ENABLE (bit 9) must remain

low this entire time to ensure proper operation of the

self test.

USE OF A10 AND A10IN

The standard configuration of the ACT7005/6

Series divides the INTERNAL RAM into separate

RECEIVE and TRANSMIT sections. For this

configuration A10 is connected to A10IN. When A10

is high, it addresses the TRANSMIT section; when

low, the RECEIVE sections. A10IN is the address

input to the INTERNAL RAM.

The interface may be configured with one common

section for both RECEIVE and TRANSMIT data. To

configure this, A10 is not connected, and A10IN is

fixed at either a logic high or low. This bit can also be

controlled by the subsystem to provide double

buffering of the contents of common RAM section for

receive and transmit data. If A10 and A10IN are not

directly connected together but gated together, then

no more than 100nsec of propagation delay should

be introduced.

NON-REGISTER OPERATIONAL

COMMANDS

There are six operational commands that are not

are summarized in Table 8. The two execute

operations are dependent on the contents of the

OPERATION register. The address codes for all the

operational commands are summarized in the 8 bit

and 16 bit l/O OPERATIONAL tables.

OPTIONAL STATUS WORD CONTROL

Message Error Bit

The ACT7005/6 monitors all receptions for errors

and sets the Message Error Bit as prescribed in

MIL-STD-1553B. The subsystem designer may,

however, exercise the option of monitoring for illegal

commands and forcing the Message Error Bit to be

set.

The word count and subaddress lines for the

current command are valid when INCMD goes low.

The subsystem must then determine whether or not

the word count or subaddress is to be considered

illegal by the RT. If either of them is considered

illegal, the subsystem must produce a

negative-going pulse called MEREQ. The

negative-going edge of MEREQ must occur within

500 nSec of the falling edge of INCMD .

Subsystem Flag and Terminal Flag Bits

The conditions that cause the Subsystem Flag and

Terminal Flag Bits in the Status Word to be reset

may be controlled by the subsystem using the

ENABLE, BIT DECODE, NEXT STATUS, and

STATUS UPDATE inputs. If ENABLE is inactive

(high), then the Terminal Flag and Subsystem Flag

behavior is the same as described below: (i.e. the

other three option lines are disabled).

Subsystem Flag Bit: This bit is reset to logic

zero by a power up initialization or the servicing of

a legal mode command to reset the remote

terminal (code 01000).

This bit shall be set in the current status register

if the subsystem error line, SSERR, from the

subsystem ever goes active low. This bit shall

also be set if an RT/subsystem handshaking

failure occurs. This bit, once set, shall be

repeatedly set until the detected error condition is

known to be no longer present.

Terminal Flag Bit: This bit is reset to logic zero

by a power up initialization or the servicing of a

legal mode command to reset the remote

terminal (code 01000). This bit can be set to logic

one in the current status register in four possible

ways:

a) If the RX detects any message encoding

or content error in the terminals

transmission. A loop test failure, LTFAIL,

will be signalled which shall cause the

Terminal Flag to be set and the

transmission aborted.

b) If a transmitter timeout occurs while the

terminal is transmitting.

c) If a remote terminal self test fails.

d) If there is a parity error in the hard wired

address to the RX chip.

This bit, once set, shall be repeatedly set until

the detected error condition is known to be no

longer present. The transmission of this bit as a

logic one can be inhibited by a legal mode

command to inhibit terminal flag bit (code 00110).

Similarly, this inhibit can be removed by a mode

command to override inhibit terminal flag bit

(code 00111), a power up initialization or a legal

mode command to reset remote terminal (code

01000).

If ENABLE is held low, then the three options

ACT7006 数据表(PDF) 11 Page - Aeroflex Circuit Technology

ACT7006 数据表(HTML) 11 Page - Aeroflex Circuit Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

数据表下载