Aeroflex Circuit Technology

SCD7005 REV B 8/2/01

Plainview NY (516) 694-6700

17

Operation

RD

WT

DS

AD3

AD2

AD1

AD0

BC AND RT MODE

No Operation-l/O Bus Tri-stated

x

x

1

x

x

x

x

Read Operation Reg. High Byte

*P

1000

01

Read Operation Reg. Low Byte

P

1000

00

Write Operation Reg. High Byte

1

P

0

0

0

0

1

Write Operation Reg. Low Byte

1

P

0

0

0

0

0

Read Output FIFO (High Byte First)

P

1

0

1

1

1

0

Write Input FIFO (High Byte First)

1

P

0

1

1

1

0

Execute Operation (Load/Unload RAM)

1

P

0

1

0

0

0

Execute Operation with Repeat

1

P

0

1

0

1

0

Reset Input FIFO

1

P

0

1

0

1

1

Reset Output FIFO

1

P

0

1

1

0

1

Reset Input and Output FIFOS

1

P

0

1

1

0

0

RT MODE ONLY

Read RT Command Word Reg. High Byte

P

1

0

0

1

0

1

Read RT Command Word Reg. LowByte

P

1

0

0

1

0

0

Read Receive Command Reg. High Byte

P

1

0

0

0

1

1

Read Receive Command Reg. LowByte

P

1

0

0

0

1

0

Read SYNC Data Reg. High Byte

P

1

0

0

1

1

1

Read SYNC Data Reg. Low Byte

P

1

0

0

1

1

0

Write Vector Word Reg. High Byte

1

P

0

0

1

1

1

Write Vector Word Reg. Low Byte

1

P

0

0

1

1

0

*P = Active Low Strobe

Note: When operating in 8-bit mode it is recommended that FIFO access be confined to even

numbers of Read or Write operations only. Failure to conform to this can result in incorrect data being

transferred to internal RAM.

BC MODE ONLY

Read Status Word #1 Reg. High Byte

P

1000

11

Read Status Word #1 Reg. Low Byte

P

1000

10

Read Status Word #2/RMD Reg. High Byte

P

1001

11

Read Status Word #2/RMD Reg. Low Byte

P

1001

10

Write Command Word #1 Reg. High Byte

1

P

0

0

0

1

1

Write Command Word #1 Reg. Low Byte

1

P

0

0

0

1

0

Write Command Word #2/AMD Reg. High Byte

1

P

0

0

1

1

1

Write Command Word #2/AMD Reg. Low Byte

1

P

0

0

1

1

0

Trigger Transaction

1

P

010

01

Table 9 – 8-Bit Mode I/O Operations