ADP5586ACBZ-00-R7 datasheet(34/44 Pages) AD

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ADP5586

Data Sheet

Rev. 0 | Page 34 of 44

RESET_CFG, Register 0x2E

Table 55. RESET_CFG Bit Descriptions

Bits

Bit Name

Access

Description

RESET_POL

Read/write

Sets the polarity of the RESET_OUT signal.

0 = RESET_OUT is active low.

1 = RESET_OUT is active high.

RST_PASSTHRU_EN

Read/write

Allows the RST pin to override (OR with) the RESET_OUT signal.

[5:2]

RESET_TRIG_TIME[3:0]

Read/write

Defines the length of time that the reset events must be active before a RESET_OUT

signal is generated. All events must be active at the same time for the same duration.

0000 = immediate.

0001 = 1.0 sec.

0010 = 1.5 sec.

0011 = 2.0 sec.

0100 = 2.5 sec.

0101 = 3.0 sec.

0110 = 3.5 sec.

0111 = 4.0 sec.

1000 = 5.0 sec.

1001 = 6.0 sec.

1010 = 7.0 sec.

1011 = 8.0 sec.

1100 = 9.0 sec.

1101 = 10.0 sec.

1110 = 11.0 sec.

1111 = 12.0 sec.

[1:0]

RESET_PULSE_WIDTH[1:0]

Read/write

Defines the pulse width of the RESET_OUT signal.

00 = 500 μs.

01 = 1 ms.

10 = 2 ms.

11 = 10 ms.

PULSE_GEN_1_DELAY, Register 0x2F

Table 56. PULSE_GEN_1_DELAY Bit Descriptions

Bits

Bit Name

Access

Description

[7:0]

PULSE_GEN_1_DELAY[7:0]

Read/write

Defines initial delay from the first clock of the first enable of Pulse Generator 1.

Delay is defined as the number of clock cycles of the chosen period clock speed

(see Register 0x35). For example,

PULSE_GEN_1_DELAY

PULSE_GEN_1_PRD_CLK

0000 0000

0 ms

0000 0001

125 ms

0000 0010

250 ms

0000 0011

375 ms

0000 0100

500 ms

…

1111 1110

254 ms

31.750 sec

1111 1111

255 ms

31.875 sec

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