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ADP5586ACBZ-00-R7 数据表(PDF) 14 Page - Analog Devices

部件名 ADP5586ACBZ-00-R7
功能描述  Keypad Decoder and I/O Port Expander
PDF  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5586ACBZ-00-R7 数据表(HTML) 14 Page - Analog Devices

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ADP5586
Data Sheet
Rev. 0 | Page 14 of 44
LOGIC BLOCK
Several of the ADP5586 input/output lines can be used as inputs
and outputs for implementing some common logic functions.
The R1, R2, and R3 input/output pins can be used as inputs,
and the R0 input/output pin can be used as an output for the
logic block. When the R1, R2, and R3 input lines are used, the
GPIO_4_INP_EN, GPIO_3_INP_EN, and GPIO_2_INP_EN
bits (Register 0x29, Bits[3:1]) must be enabled to accept inputs.
When the R0 pin is used as an output for the logic block, the
GPIO_1_OUT_EN bit (Register 0x27, Bit 0) must be enabled.
The outputs from the logic block can be configured to generate
interrupts. They can also be configured to generate events on
the FIFO.
Figure 19 shows a detailed diagram of the internal makeup of
the logic block, illustrating the possible logic functions that can
be implemented.
GPI EVENT
KEY EVENT
LOGIC EVENT
(R1)
LA
LC
LB
LA_INV
D
CLR
Q
SET
LB_INV
LC_INV
FF_SET
FF_CLR
R3_EXTEND_CFG
LOGIC_SEL[2:0]
LY_INV
(R2)
(R3)
LOGIC BLOCK
LY (R0)
LOGIC_INT
LOGIC_INT_LEVEL
LOGIC_EVENT_EN
OVRFLOW_INT
EVENT_INT
RESET_TRIG_TIME[3:0]
RESET_EVENT_A[7:0]
RESET_EVENT_B[7:0]
RESET_EVENT_C[7:0]
FIFO
EC[4:0]
LOGIC
EVENT/INT
GENERATOR
I2C BUSY
FIFO
UPDATE
Figure 18. Logic Block Overview
LA_INV
MUX
000
001
SEL[2:0]
OUT
010
011
100
101
110
111
SEL
OUT
0
1
GND
AND
OR
XOR
FF
IN_LA
IN_LB
IN_LC
LA
LA
LA
IN_LA
SEL
OUT
0
1
AND
IN_LA
IN_LB
IN_LC
R3_EXTEND_CFG = 1
LOGIC_SEL[2:0]
LY_INV
SEL
OUT
0
1
LY
LY
LY
LB_INV
SEL
OUT
0
1
LB
LB
LB
IN_LB
LC_INV
SEL
OUT
0
1
LC
LC
LC
IN_LC
FF_SET
FF_CLR
SEL
OUT
0
1
OR
IN_LA
IN_LB
IN_LC
AND
AND
OR
OR
SEL
OUT
0
1
XOR
IN_LA
IN_LB
IN_LC
IN_LA
IN_LB
IN_LC
XOR
XOR
D
CLR
Q
SET
0
1
SEL
OUT
FF
Figure 19. Logic Block Internal Makeup



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