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ADP5586ACBZ-00-R7 数据表(PDF) 35 Page - Analog Devices

部件名 ADP5586ACBZ-00-R7
功能描述  Keypad Decoder and I/O Port Expander
PDF  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5586ACBZ-00-R7 数据表(HTML) 35 Page - Analog Devices

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Data Sheet
ADP5586
Rev. 0 | Page 35 of 44
PULSE_GEN_1_PERIOD, Register 0x30
Table 57. PULSE_GEN_1_PERIOD Bit Descriptions
Bits
Bit Name
Access
Description
[7:0]
PULSE_GEN_1_PERIOD[7:0]
Read/write
Defines period of Pulse Generator 1. Period is defined as the number of clock cycles
of the chosen period clock speed (see Register 0x35). For example,
PULSE_GEN_1_PERIOD
PULSE_GEN_1_PRD_CLK
0
1
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
1111 1110
1111 1111
0 ms
1 ms
2 ms
3 ms
4 ms
254 ms
255 ms
0 ms
125 ms
250 ms
375 ms
500 ms
31.750 sec
31.875 sec
PULSE_GEN_1_ON_TIME, Register 0x31
Table 58. PULSE_GEN_1_ON_TIME Bit Descriptions
Bits
Bit Name
Access
Description
[7:0]
PULSE_GEN_1_ON_TIME[7:0]
Read/write
Defines on time of Pulse Generator 1. On time is defined as the number of clock
cycles of the chosen clock speed (see Register 0x35). For example,
PULSE_GEN_1_ON_TIME
PULSE_GEN_1_ON_CLK
0
1
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
1111 1110
1111 1111
0 ms
1 ms
2 ms
3 ms
4 ms
254 ms
255 ms
0 ms
125 ms
250 ms
375 ms
500 ms
31.750 sec
31.875 sec
PULSE_GEN_2_DELAY, Register 0x32
Table 59. PULSE_GEN_2_DELAY Bit Descriptions
Bits
Bit Name
Access
Description
[7:0]
PULSE_GEN_2_DELAY[7:0]
Read/write
Defines initial delay from the first clock of the first enable of Pulse Generator 2.
Delay is defined as the number of clock cycles of the chosen period clock speed
(see Register 0x35). For example,
PULSE_GEN_2_DELAY
PULSE_GEN_2_PRD_CLK
0
1
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
1111 1110
1111 1111
0 ms
1 ms
2 ms
3 ms
4 ms
254 ms
255 ms
0 ms
125 ms
250 ms
375 ms
500 ms
31.750 sec
31.875 sec



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